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1. 发明授权

US08829570B2 Switching device for heterojunction integrated circuits and methods of forming the same 有权
标题翻译：用于异质结集成电路的开关装置及其形成方法
公开(公告)号：US08829570B2
公开(公告)日：2014-09-09
申请号：US13416152
申请日：2012-03-09
申请人： Srivatsan Parthasarathy , Javier A. Salcedo , Shuyun Zhang
发明人： Srivatsan Parthasarathy , Javier A. Salcedo , Shuyun Zhang
IPC分类号： H01L33/00
CPC分类号： H01L27/0262
摘要： A switching device for heterojunction integrated circuits is disclosed. According to one aspect, the switching device is configured to protect a circuit from an electro-static discharge (ESD) event. The switching device includes a second base contact region that is configured to be electrically floating, a first base contact region and a collector contact region that are coupled to a first input terminal of the switching device, and an emitter contact region that is coupled to a second input terminal of the switching device. Due in part to capacitive coupling between the first base contact region and the second base contact region, the switching device exhibits a low transient trigger voltage and a fast response to ESD events. Further, the switching device exhibits a high DC trigger voltage (for example, greater than 20V), while maintaining relatively low leakage current during operation (for example, less than about 0.5 μA at 20V DC.
摘要翻译：公开了一种用于异质结集成电路的开关装置。根据一个方面，开关装置被配置为保护电路免受静电放电（ESD）事件的影响。开关器件包括被配置为电浮置的第二基极接触区域，耦合到开关器件的第一输入端子的第一基极接触区域和集电极接触区域以及耦合到开关器件的发射极接触区域第二输入端子。部分地由于第一基极接触区域和第二基极接触区域之间的电容耦合，开关器件表现出低瞬态触发电压和对ESD事件的快速响应。此外，开关器件表现出高直流触发电压（例如，大于20V），同时在操作期间保持较低的漏电流（例如，在20V DC时小于约0.5μA）。

2. 发明申请

US20130320498A1 LOW VOLTAGE PROTECTION DEVICES FOR PRECISION TRANSCEIVERS AND METHODS OF FORMING THE SAME 有权
标题翻译：用于精密收发器的低电压保护装置及其形成方法
公开(公告)号：US20130320498A1
公开(公告)日：2013-12-05
申请号：US13486885
申请日：2012-06-01
申请人： Javier A. Salcedo
发明人： Javier A. Salcedo
IPC分类号： H01L29/73
CPC分类号： H01L29/747 , H01L27/0259 , H01L27/0921
摘要： A bi-directional protection device includes a bi-directional NPN bipolar transistor including an emitter/collector formed from a first n-well region, a base formed from a p-well region, and a collector/emitter formed from a second n-well region. P-type active regions are formed in the first and second n-well regions to form a PNPNP structure, which is isolated from the substrate using dual-tub isolation consisting of an n-type tub and a p-type tub. The dual-tub isolation prevents induced latch-up during integrated circuit powered stress conditions by preventing the wells associated with the PNPNP structure from injecting carriers into the substrate. The size, spacing, and doping concentrations of active regions and wells associated with the PNPNP structure are selected to provide fine-tuned control of the trigger and holding voltage characteristics to enable the bi-directional protection device to be implemented in high voltage applications using low voltage precision interface signaling.
摘要翻译：双向保护装置包括双极NPN双极晶体管，其包括由第一n阱区域形成的发射极/集电极，由p阱区域形成的基极和由第二n阱形成的集电极/发射极地区。在第一和第二n阱区域中形成P型有源区，以形成PNPNP结构，该PNPNP结构使用由n型槽和p型槽构成的双槽隔离与基板隔离。双槽隔离通过防止与PNPNP结构相关联的阱将载流子注入到衬底中来防止在集成电路供电的应力条件期间引起的闩锁。选择与PNPNP结构相关联的有源区和阱的尺寸，间距和掺杂浓度以提供对触发和保持电压特性的微调控制，以使双向保护装置能够在使用低电压的高电压应用中实现电压精密接口信号。

3. 发明申请

US20130032882A1 BI-DIRECTIONAL BLOCKING VOLTAGE PROTECTION DEVICES AND METHODS OF FORMING THE SAME 有权
标题翻译：双向阻塞电压保护装置及其形成方法
公开(公告)号：US20130032882A1
公开(公告)日：2013-02-07
申请号：US13198208
申请日：2011-08-04
申请人： Javier A. Salcedo , Michael Lynch , Brian Moane
发明人： Javier A. Salcedo , Michael Lynch , Brian Moane
IPC分类号： H01L27/06 , H01L21/8249
CPC分类号： H01L27/0262 , H01L27/0921
摘要： Bi-directional blocking voltage protection devices and methods of forming the same are disclosed. In one embodiment, a protection device includes an n-well and first and second p-wells disposed on opposite sides of the n-well. The first p-well includes a first P+ region and a first N+ region and the second p-well includes a second P+ region and second N+ region. The device further includes a third P+ region disposed along a boundary of the n-well and the first p-well and a fourth P+ region disposed along a boundary of the n-well and the second p-well. A first gate is disposed between the first N+ region and the third P+ region and a second gate is disposed between the second N+ region and the fourth P+ region. The device provides bi-directional blocking voltage protection during high energy stress events, including in applications operating at very low to medium swing voltages.
摘要翻译：公开了双向阻断电压保护装置及其形成方法。在一个实施例中，保护装置包括n阱以及设置在n阱的相对侧上的第一和第二p阱。第一p阱包括第一P +区和第一N +区，第二p阱包括第二P +区和第二N +区。该装置还包括沿着n阱和第一p阱的边界设置的第三P +区和沿着n阱和第二p阱的边界设置的第四P +区。第一栅极设置在第一N +区域和第三P +区域之间，第二栅极设置在第二N +区域和第四P +区域之间。该器件在高能量应力事件期间提供双向阻断电压保护，包括在非常低至中等摆幅电压下工作的应用。

4. 发明申请

US20120306013A1 METAL OXIDE SEMICONDUCTOR OUTPUT CIRCUITS AND METHODS OF FORMING THE SAME 有权
标题翻译：金属氧化物半导体输出电路及其形成方法
公开(公告)号：US20120306013A1
公开(公告)日：2012-12-06
申请号：US13152867
申请日：2011-06-03
申请人： Colm Donovan , Javier A. Salcedo
发明人： Colm Donovan , Javier A. Salcedo
IPC分类号： H01L29/78 , H01L21/8238 , H01L27/092
CPC分类号： H01L27/0285
摘要： Metal oxide semiconductor (MOS) protection circuits and methods of forming the same are disclosed. In one embodiment, an integrated circuit includes a pad, a p-type MOS (PMOS) transistor, and first and second n-type MOS (NMOS) transistors. The first NMOS transistor includes a drain, a source and a gate electrically connected to the pad, a first supply voltage, and a drain of the PMOS transistor, respectively. The second NMOS transistor includes a gate, a drain, and a source electrically connected to a bias node, a second supply voltage, and a source of the PMOS transistor, respectively. The source of the second NMOS transistor is further electrically connected to a body of the PMOS transistor so as to prevent a current flowing from the drain of the PMOS transistor to the second supply voltage through the body of PMOS transistor when a transient signal event is received on the pad.
摘要翻译：公开了金属氧化物半导体（MOS）保护电路及其形成方法。在一个实施例中，集成电路包括焊盘，p型MOS（PMOS）晶体管以及第一和第二n型MOS（NMOS）晶体管。第一NMOS晶体管分别包括漏极，源极和电连接到焊盘的栅极，PMOS晶体管的第一电源电压和漏极。第二NMOS晶体管分别包括电连接到偏置节点，第二电源电压和PMOS晶体管的源极的栅极，漏极和源极。第二NMOS晶体管的源极进一步电连接到PMOS晶体管的主体，以便当接收到瞬态信号事件时，防止电流从PMOS晶体管的漏极流过PMOS晶体管的主体在垫上。

5. 发明授权

US08582261B2 Apparatus and method for electronic circuit protection 有权
标题翻译：电子电路保护装置及方法
公开(公告)号：US08582261B2
公开(公告)日：2013-11-12
申请号：US13598293
申请日：2012-08-29
申请人： Javier A. Salcedo , Colin McHugh
发明人： Javier A. Salcedo , Colin McHugh
IPC分类号： H02H9/00
CPC分类号： H02H9/046
摘要： Apparatus and methods for electronic circuit protection are disclosed. In one embodiment, an actively-controlled protection circuit includes a detector, a timer, a current source and a latch. The detector is configured to generate a detection signal when the detector determines that a transient signal satisfies a first signaling condition. The timer is configured to receive the detection signal, and to generate a current control signal. The current control signal is provided to a current source, which produces a trigger current at least partly in response to the control signal. The trigger current is provided to a node of the latch, thereby enhancing the conductivity modulation of the latch and selectively controlling the activation voltage of the latch.
摘要翻译：公开了用于电子电路保护的装置和方法。在一个实施例中，主动控制的保护电路包括检测器，定时器，电流源和锁存器。检测器被配置为当检测器确定瞬态信号满足第一信号条件时产生检测信号。定时器被配置为接收检测信号，并产生电流控制信号。电流控制信号被提供给电流源，其至少部分地响应于控制信号而产生触发电流。触发电流被提供给锁存器的节点，从而增强锁存器的电导率调制并选择性地控制锁存器的激活电压。

6. 发明申请

US20130242448A1 APPARATUS AND METHOD FOR PROTECTION OF PRECISION MIXED-SIGNAL ELECTRONIC CIRCUITS 有权
标题翻译：用于保护精密混合信号电子电路的装置和方法
公开(公告)号：US20130242448A1
公开(公告)日：2013-09-19
申请号：US13423720
申请日：2012-03-19
申请人： Javier A. Salcedo , Srivatsan Parthasarathy
发明人： Javier A. Salcedo , Srivatsan Parthasarathy
IPC分类号： H02H3/22
CPC分类号： H01L27/0262 , H01L21/8222 , H01L27/0259
摘要： Apparatus and methods for precision mixed-signal electronic circuit protection are provided. In one embodiment, an apparatus includes a p-well, an n-well, a poly-active diode structure, a p-type active region, and an n-type active region. The poly-active diode structure is formed over the n-well, the p-type active region is formed in the n-well on a first side of the poly-active diode structure, and the n-type active region is formed along a boundary of the p-well and the n-well on a second side of the poly-active diode structure. During a transient electrical event the apparatus is configured to provide conduction paths through and underneath the poly-active diode structure to facilitate injection of carriers in the n-type active region. The protection device can further include another poly-active diode structure formed over the p-well to further enhance carrier injection into the n-type active region.
摘要翻译：提供了精密混合信号电子电路保护的装置和方法。在一个实施例中，一种装置包括p阱，n阱，多有源二极管结构，p型有源区和n型有源区。多极二极管结构形成在n阱上，p型有源区形成在多功能二极管结构的第一侧上的n阱中，并且n型有源区沿着在多活性二极管结构的第二侧上的p阱和n阱的边界。在瞬态电气事件期间，该装置被配置为提供穿过多功能二极管结构之间和之下的导电路径，以便于在n型有源区域中注入载流子。保护装置还可以包括在p阱上形成的另一个多有源二极管结构，以进一步增强对n型有源区的载流子注入。

7. 发明申请

US20130234209A1 SWITCHING DEVICE FOR HETEROJUNCTION INTEGRATED CIRCUITS AND METHODS OF FORMING THE SAME 有权
标题翻译：异步集成电路的切换装置及其形成方法
公开(公告)号：US20130234209A1
公开(公告)日：2013-09-12
申请号：US13416152
申请日：2012-03-09
申请人： Srivatsan Parthasarathy , Javier A. Salcedo , Shuyun Zhang
发明人： Srivatsan Parthasarathy , Javier A. Salcedo , Shuyun Zhang
IPC分类号： H01L29/737 , H01L21/331
CPC分类号： H01L27/0262
摘要： A switching device for heterojunction integrated circuits is disclosed. According to one aspect, the switching device is configured to protect a circuit from an electro-static discharge (ESD) event. The switching device includes a second base contact region that is configured to be electrically floating, a first base contact region and a collector contact region that are coupled to a first input terminal of the switching device, and an emitter contact region that is coupled to a second input terminal of the switching device. Due in part to capacitive coupling between the first base contact region and the second base contact region, the switching device exhibits a low transient trigger voltage and a fast response to ESD events. Further, the switching device exhibits a high DC trigger voltage (for example, greater than 20V), while maintaining relatively low leakage current during operation (for example, less than about 0.5 μA at 20V DC.
摘要翻译：公开了一种用于异质结集成电路的开关装置。根据一个方面，开关装置被配置为保护电路免受静电放电（ESD）事件的影响。开关器件包括被配置为电浮置的第二基极接触区域，耦合到开关器件的第一输入端子的第一基极接触区域和集电极接触区域以及耦合到开关器件的发射极接触区域第二输入端子。部分地由于第一基极接触区域和第二基极接触区域之间的电容耦合，开关器件表现出低瞬态触发电压和对ESD事件的快速响应。此外，开关器件表现出高直流触发电压（例如，大于20V），同时在操作期间保持相对较低的漏电流（例如，在20V DC时小于约0.5μA）。

8. 发明授权

US08519432B2 Semiconductor switch 有权
标题翻译：半导体开关
公开(公告)号：US08519432B2
公开(公告)日：2013-08-27
申请号：US12079841
申请日：2008-03-27
申请人： Jeffrey G. Barrow , Javier A. Salcedo , A. Paul Brokaw
发明人： Jeffrey G. Barrow , Javier A. Salcedo , A. Paul Brokaw
IPC分类号： H01L29/66
CPC分类号： H01L29/745 , H01L29/7408 , H01L29/7455
摘要： A semiconductor switch comprises a PNPN structure arranged to provide an SCR-like functionality, and a MOS gate structure, preferably integrated on a common substrate. The switch includes ohmic contacts for the MOS gate, and for the cathode and gate regions of the PNPN structure; the anode contact is intrinsic. A fixed voltage is typically applied to an external node. The MOS gate structure allows current to be conducted between the external node and the intrinsic anode when on, and the PNPN structure conducts the current from the anode to the cathode when an appropriate voltage is applied to the gate contact. Regenerative feedback keeps the switch on once it begins to conduct. The MOS gate inhibits the flow of current between the external node and anode—and thereby turns off the switch—when off. When on, the MOS gate's channel resistance serves as a ballast resistor.
摘要翻译：半导体开关包括被布置为提供类SCR功能的PNPN结构，以及优选地集成在公共基板上的MOS栅极结构。该开关包括用于MOS栅极的欧姆接触，以及用于PNPN结构的阴极和栅极区域; 阳极接触是固有的。固定电压通常被施加到外部节点。 MOS栅极结构允许在导通时在外部节点和本征阳极之间传导电流，并且当适当的电压施加到栅极触点时，PNPN结构将电流从阳极传导到阴极。再生反馈一旦开始进行，就保持开关状态。 MOS门禁止外部节点和阳极之间的电流流动，从而在关闭时关闭开关。当导通时，MOS栅极的沟道电阻用作镇流电阻。

9. 发明申请

US20120008242A1 APPARATUS AND METHOD FOR ELECTRONIC CIRCUIT PROTECTION 有权
标题翻译：电子电路保护的装置和方法
公开(公告)号：US20120008242A1
公开(公告)日：2012-01-12
申请号：US12832820
申请日：2010-07-08
申请人： Javier A. Salcedo
发明人： Javier A. Salcedo
IPC分类号： H02H9/00 , H01L21/331 , H01L21/8222 , H01L27/06
CPC分类号： H01L27/0259
摘要： Apparatuses and methods for electronic circuit protection are disclosed. In one embodiment, an apparatus comprises an internal circuit electrically connected between a first node and a second node, and a protection circuit electrically connected between the first node and the second node and configured to protect the internal circuit from transient electrical events. The protection circuit comprises a bipolar transistor having an emitter connected to the first node, a base connected to a third node, and a collector connected to a fourth node. The protection circuit further comprises a first diode electrically connected between the third node and the fourth node, and a second diode electrically connected between the second node and the fourth node. The first diode is an avalanche breakdown diode having an avalanche breakdown voltage lower than or about equal to a breakdown voltage associated with the base and the collector of the bipolar transistor.
摘要翻译：公开了用于电子电路保护的装置和方法。在一个实施例中，一种装置包括电连接在第一节点和第二节点之间的内部电路，以及电连接在第一节点和第二节点之间并被配置为保护内部电路免受瞬态电气事件的保护电路。保护电路包括双极晶体管，其具有连接到第一节点的发射极，连接到第三节点的基极和连接到第四节点的集电极。保护电路还包括电连接在第三节点和第四节点之间的第一二极管，以及电连接在第二节点和第四节点之间的第二二极管。第一二极管是雪崩击穿二极管，其雪崩击穿电压低于或约等于与双极晶体管的基极和集电极相关的击穿电压。

10. 发明授权

US08637899B2 Method and apparatus for protection and high voltage isolation of low voltage communication interface terminals 有权
标题翻译：低压通信接口端子的保护和高压隔离方法和装置
公开(公告)号：US08637899B2
公开(公告)日：2014-01-28
申请号：US13492677
申请日：2012-06-08
申请人： Javier A. Salcedo
发明人： Javier A. Salcedo
IPC分类号： H01L29/66
CPC分类号： H01L27/0262
摘要： A high voltage isolation protection device for low voltage communication interface systems in mixed-signal high voltage electronic circuit is disclosed. According to one aspect, the protection device includes a semiconductor structure configured to provide isolation between low voltage terminals and protection from transient events. The protection device includes a thyristor having an anode, a cathode, and a gate, and a thyristor cathode-gate control region that is built into the protection device. The protection device is configured to provide multiple built-in path-up to power-high terminals and path-down to power-low terminals at different voltage levels. The protection device also includes independently built-in discharge paths to the common substrate that is connected to a different power-low voltage reference. The conduction paths may be built into a single structure with dual isolation regions. As a result, the protection device enables superior robustness and compact protection solutions for smart power applications.
摘要翻译：公开了一种用于混合信号高压电子电路中的低压通信接口系统的高压隔离保护装置。根据一个方面，保护装置包括被配置为提供低电压端子之间的隔离并且防止瞬态事件的半导体结构。保护装置包括具有阳极，阴极和栅极的晶闸管和内置在保护装置中的晶闸管阴极 - 栅极控制区域。保护装置被配置为在不同的电压电平下向功率上限端子提供多个内置通路，并向下降到低功耗端子。保护装置还包括连接到不同功率低电压基准的独立内置到公共基板的放电路径。传导路径可以内置在具有双隔离区域的单个结构中。因此，保护装置可为智能电源应用提供卓越的鲁棒性和紧凑的保护解决方案。

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