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1. 发明授权

US07178120B2 Method for performing timing closure on VLSI chips in a distributed environment 失效
标题翻译：在分布式环境中对VLSI芯片进行定时关闭的方法
公开(公告)号：US07178120B2
公开(公告)日：2007-02-13
申请号：US10338929
申请日：2003-01-08
申请人： Nathaniel Hieter , David J. Hathaway , Prabhakar Kudva , David S. Kung , Leon Stok
发明人： Nathaniel Hieter , David J. Hathaway , Prabhakar Kudva , David S. Kung , Leon Stok
IPC分类号： G06H17/50 , G06H9/45
CPC分类号： G06F17/505 , G06F17/5072
摘要： A method for performing timing closure on VLSI chips in a distributed environment is described. Abstracting the physical and timing resources of a chip and providing an asynchronous method of updating that abstraction allows multiple partitions of a chip to be optimized concurrently. A global view of physical and timing resources is supplied to local optimizations which are applied concurrently to achieve timing closure. Portions of the hierarchy are optimized in separate processes. Partitioning of the chip is performed along hierarchical lines, with each process owning a single partition in the hierarchy. The processes may be executed by a single computer, or spread across multiple computers in a local network. While optimizations performed by a single process are only applied to its given portion of the hierarchy, decisions are made in the context of the entire hierarchy. These optimizations include placement, synthesis, and routing. The present method can also be expanded to include other resources, such as routing resource, power supply current, power/thermal budget, substrate noise budget, and the like, all of which being able to be similarly abstracted and shared.
摘要翻译：描述了在分布式环境中对VLSI芯片执行定时闭合的方法。提取芯片的物理和定时资源并提供更新抽象的异步方法，可以同时优化芯片的多个分区。将物理和时序资源的全局视图提供给同时实现时序收敛的局部优化。层次结构的部分在单独的进程中进行了优化。芯片的分区按照层次线执行，每个进程在层次结构中拥有单个分区。这些过程可以由单个计算机执行，或者分布在本地网络中的多个计算机上。虽然单个进程执行的优化仅适用于其给定的层次结构部分，但是在整个层次结构的上下文中进行决策。这些优化包括放置，合成和路由。本方法还可以扩展到包括路由资源，电源电流，功率/热预算，衬底噪声预算等其他资源，所有这些资源都能被类似地抽象和共享。

2. 发明授权

US07853917B2 System for building binary decision diagrams efficiently in a structural network representation of a digital circuit 有权
标题翻译：用于在数字电路的结构网络表示中有效地构建二进制决策图的系统
公开(公告)号：US07853917B2
公开(公告)日：2010-12-14
申请号：US11963267
申请日：2007-12-21
申请人： Viresh Paruthi , Christian Jacobi , Geert Janssen , Jiazhao Xu , Kai Oliver Weber
发明人： Viresh Paruthi , Christian Jacobi , Geert Janssen , Jiazhao Xu , Kai Oliver Weber
IPC分类号： G06H17/50
CPC分类号： G06F17/30958 , G06F17/504 , Y10S707/99942
摘要： A method, system and computer program product for building decision diagrams efficiently in a structural network representation of a digital circuit using a dynamic resource constrained and interleaved depth-first-search and modified breadth-first-search schedule is disclosed. The method includes setting a first size limit for a first set of one or more m-ary decision representations describing a logic function and setting a second size limit for a second set of one or more m-ary decision representations describing a logic function. The first set of m-ary decision representations of the logic function is then built with one of the set of a depth-first technique or a breadth-first technique until the first size limit is reached, and a second set of m-ary decision representations of the logic function is built with the other technique until the second size limit is reached. In response to determining that a union of first set and the second set of m-ary decision representations do not describe the logic function, the first and second size limits are increased, and the steps of building the first and second set are repeated. In response to determining that the union of the first set of m-ary decision representations and the second set of m-ary decision representations describe the logic function, the union is reported.
摘要翻译：公开了一种用于在使用动态资源约束和交织的深度优先搜索和修改的宽度优先搜索时间表的数字电路的结构网络表示中有效地构建决策图的方法，系统和计算机程序产品。该方法包括：对描述逻辑功能的一个或多个多元决策表示的第一集合设置第一大小限制，并为描述逻辑功能的一个或多个虚拟决策表示的第二组设置第二大小限制。然后，利用深度优先技术或宽度优先技术的集合之一构建逻辑功能的第一组m元决定表示，直到达到第一大小限制，并且第二组m元决定使用其他技术构建逻辑功能的表示，直到达到第二个大小限制。响应于确定第一集合和第二组m元决定表示的并集不描述逻辑函数，增加第一和第二大小限制，并且重复构建第一集合和第二集合的步骤。响应于确定第一组m元决策表示和第二组m元决策表示的并集描述逻辑函数，报告联合。

3. 发明授权

US5910899A Method for performing floorplan timing analysis using multi-dimensional feedback in a spreadsheet with computed hyperlinks to physical layout graphics and integrated circuit made using same 失效
标题翻译：使用电子表格中的多维反馈来执行平面布置图时序分析的方法，其中计算出的物理布局图形的超链接以及使用它们的集成电路
公开(公告)号：US5910899A
公开(公告)日：1999-06-08
申请号：US736920
申请日：1996-10-25
申请人： Carlo E. Barrientos
发明人： Carlo E. Barrientos
IPC分类号： G06F17/50 , G06H17/50
CPC分类号： G06F17/5031 , G06F17/5072
摘要： A computer-implemented method for aiding in the design of an integrated circuit (IC) floorplan. The method comprises receiving a netlist, physical layout information, and timing constraints of the IC and performing timing analysis of the signal paths of the IC. The user selects the set of nets to by analyzed. The timing analysis comprises calculating net delays as a function of the length of the signal paths. The timing analysis further comprises calculating slack times by subtracting from the clock cycle time of the IC the sum of the driven at timing constraint, the needed by timing constraint, and the net delay. Paths which have a slack time greater than a slack failure value are passing nets and paths which have a slack time greater than a slack failure value are failing nets. The slack failure value is user-specifiable and defaults to zero. The method further comprises displaying in a spreadsheet the timing constraints, net delays, and slack times for each path selected, thus providing the designer with complex multi-dimensional feedback. The feedback for each path in the spreadsheet is accompanied by a hyperlink button, which the designer selects in order to graphically display the path on a graphical view of the floorplan. Thus the designer is enabled to relate the non-graphical timing information to a graphical display of the paths and apply his or her intuitive knowledge to make necessary changes to the floorplan. The timing information is further summarily displayed in a histogram, thus providing visual feedback regarding the timing quality of the floorplan. The method provides means for the designer to display failing paths, passing paths, all paths, and paths skipped in timing analysis due to the absence of timing constraints.
摘要翻译：用于协助设计集成电路（IC）平面图的计算机实现的方法。该方法包括接收IC的网表，物理布局信息和时序约束，并执行IC的信号路径的定时分析。用户通过分析来选择网络集。定时分析包括计算作为信号路径的长度的函数的净延迟。定时分析还包括通过从IC的时钟周期时间中减去在定时约束下的驱动定时约束，定时约束所需的和净延迟的时间来计算松弛时间。具有大于松弛失效值的松弛时间的路径是通过网络和具有大于松弛失败值的松弛时间的路径是网络故障。松弛失败值是用户指定的，默认为零。该方法还包括在电子表格中显示所选择的每个路径的定时约束，净延迟和松弛时间，从而为设计者提供复杂的多维反馈。电子表格中每个路径的反馈都伴随有一个超链接按钮，设计人员选择这个按钮，以图形显示平面图的图形视图中的路径。因此，设计者能够将非图形定时信息与路径的图形显示相关联，并且应用他或她的直观知识来对平面图进行必要的改变。定时信息进一步以直方图显示，从而提供关于平面图的定时质量的视觉反馈。该方法提供了设计者在时序分析中显示故障路径，传递路径，所有路径和路径跳过的手段，因为没有时序约束。

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