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1. 发明申请

US20080201563A1 Apparatus for Improving Single Thread Performance through Speculative Processing 审中-公开
标题翻译：通过投机处理提高单线性能的装置
公开(公告)号：US20080201563A1
公开(公告)日：2008-08-21
申请号：US12110400
申请日：2008-04-28
申请人： Jason N. Dale , H. Peter Hofstee , Albert James Van Norstrand
发明人： Jason N. Dale , H. Peter Hofstee , Albert James Van Norstrand
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3824 , G06F9/3851 , G06F9/3863 , G06F9/461
摘要： An apparatus is provided for using multiple thread contexts to improve processing performance of a single thread. When an exceptional instruction is encountered, the exceptional instruction and any predicted instructions are reloaded into a buffer of a first thread context. A state of the register file at the time of encountering the exceptional instruction is maintained in a register file of the first thread context. The instructions in the pipeline are executed speculatively using a second register file in a second thread context. During speculative execution, cache misses may cause loading of data to the cache may be performed. Results of the speculative execution are written to the second register file. When a stopping condition is met, contents of the first register file are copied to the second register file and the reloaded instructions are released to the execution pipeline.
摘要翻译：提供了一种用于使用多个线程上下文来提高单个线程的处理性能的装置。当遇到异常指令时，异常指令和任何预测指令被重新加载到第一个线程上下文的缓冲区中。在遇到异常指令时，寄存器文件的状态被保存在第一个线程上下文的寄存器文件中。使用第二线程上下文中的第二寄存器文件推测地执行流水线中的指令。在推测执行期间，高速缓存未命中可能导致数据加载到缓存可能被执行。推测执行的结果将写入第二个寄存器文件。当满足停止条件时，将第一寄存器文件的内容复制到第二寄存器文件，并且重新加载的指令被释放到执行管线。

2. 发明授权

US06792524B1 System and method cancelling a speculative branch 失效
标题翻译：系统和方法取消推测分支
公开(公告)号：US06792524B1
公开(公告)日：2004-09-14
申请号：US09137653
申请日：1998-08-20
申请人： Milford John Peterson , David Andrew Schroter , Albert James Van Norstrand
发明人： Milford John Peterson , David Andrew Schroter , Albert James Van Norstrand
IPC分类号： G06F944
CPC分类号： G06F9/3842 , G06F9/3844
摘要： For each predicted branch within a processor, an entry is maintained within a branch history table. The entry within the branch history table also includes an indication of the past record for that particular branch instruction, which indicates how correct the branch prediction has been in the past. When the field value associated with the predicted branch exceeds a certain threshold, indicating that the past predictions associated with that branch instruction have been at an unacceptable level, then the speculative branch instructions dispatching is suspended for that particular branch instruction. Alternative embodiments utilize a global indicator for suspending or cancelling instruction dispatch when the frequency of previous incorrect branch predictions increases beyond a preselected threshold.
摘要翻译：对于处理器内的每个预测分支，条目保持在分支历史表中。分支历史表中的条目还包括针对该特定分支指令的过去记录的指示，其指示分支预测在过去如何正确。当与预测分支相关联的字段值超过某个阈值时，指示与该分支指令相关联的过去预测已经处于不可接受的水平，则针对该特定分支指令暂停推测分支指令分派。当先前错误分支预测的频率增加超过预选阈值时，替代实施例利用全局指示符来暂停或取消指令分派。

3. 发明授权

US08028151B2 Performance of an in-order processor by no longer requiring a uniform completion point across different execution pipelines 失效
标题翻译：通过不再需要跨不同执行管道的统一完成点来执行按顺序处理器的性能
公开(公告)号：US08028151B2
公开(公告)日：2011-09-27
申请号：US12277376
申请日：2008-11-25
申请人： Christopher Michael Abernathy , Jonathan James Dement , Ronald Hall , Albert James Van Norstrand
发明人： Christopher Michael Abernathy , Jonathan James Dement , Ronald Hall , Albert James Van Norstrand
IPC分类号： G06F9/30 , G06F9/00
CPC分类号： G06F9/3836 , G06F9/3855 , G06F9/3857 , G06F9/3863
摘要： A method, system and processor for improving the performance of an in-order processor. A processor may include an execution unit with an execution pipeline that includes a backup pipeline and a regular pipeline. The backup pipeline may store a copy of the instructions issued to the regular pipeline. The execution pipeline may include logic for allowing instructions to flow from the backup pipeline to the regular pipeline following the flushing of the instructions younger than the exception detected in the regular pipeline. By maintaining a backup copy of the instructions issued to the regular pipeline, instructions may not need to be flushed from separate execution pipelines and re-fetched. As a result, one may complete the results of the execution units to the architected state out of order thereby allowing the completion point to vary among the different execution pipelines.
摘要翻译：一种用于改善按顺序处理器的性能的方法，系统和处理器。处理器可以包括具有包括备用流水线和常规流水线的执行流水线的执行单元。备用管道可以存储发给正常管道的指令的副本。执行流水线可以包括逻辑，用于在刷新比正常流水线中检测到的异常之后的指令更新时允许指令从备用流水线流向正常流水线。通过维护发布到常规流水线的指令的备份副本，可能不需要从单独的执行流程中刷新指令并重新获取。结果，可以将执行单元的结果完成到设计状态，从而使完成点在不同执行流水线之间变化。

4. 发明申请

US20090077352A1 PERFORMANCE OF AN IN-ORDER PROCESSOR BY NO LONGER REQUIRING A UNIFORM COMPLETION POINT ACROSS DIFFERENT EXECUTION PIPELINES 失效
标题翻译：不需要长时间执行订单处理器的性能，需要通过不同执行管道的均匀完成点
公开(公告)号：US20090077352A1
公开(公告)日：2009-03-19
申请号：US12277376
申请日：2008-11-25
申请人： Christopher Michael Abernathy , Jonathan James Dement , Ronald Hall , Albert James Van Norstrand
发明人： Christopher Michael Abernathy , Jonathan James Dement , Ronald Hall , Albert James Van Norstrand
IPC分类号： G06F9/38
CPC分类号： G06F9/3836 , G06F9/3855 , G06F9/3857 , G06F9/3863
摘要： A method, system and processor for improving the performance of an in-order processor. A processor may include an execution unit with an execution pipeline that includes a backup pipeline and a regular pipeline. The backup pipeline may store a copy of the instructions issued to the regular pipeline. The execution pipeline may include logic for allowing instructions to flow from the backup pipeline to the regular pipeline following the flushing of the instructions younger than the exception detected in the regular pipeline. By maintaining a backup copy of the instructions issued to the regular pipeline, instructions may not need to be flushed from separate execution pipelines and re-fetched. As a result, one may complete the results of the execution units to the architected state out of order thereby allowing the completion point to vary among the different execution pipelines.
摘要翻译：一种用于改善按顺序处理器的性能的方法，系统和处理器。处理器可以包括具有包括备用流水线和常规流水线的执行流水线的执行单元。备用管道可以存储发给正常管道的指令的副本。执行流水线可以包括逻辑，用于在刷新比正常流水线中检测到的异常之后的指令更新时允许指令从备用流水线流向正常流水线。通过维护发布到常规流水线的指令的备份副本，可能不需要从单独的执行流程中刷新指令并重新获取。结果，可以将执行单元的结果完成到设计状态，从而使完成点在不同执行流水线之间变化。

5. 发明授权

US07475232B2 Performance of an in-order processor by no longer requiring a uniform completion point across different execution pipelines 失效
标题翻译：通过不再需要跨不同执行管道的统一完成点来执行按顺序处理器的性能
公开(公告)号：US07475232B2
公开(公告)日：2009-01-06
申请号：US11184349
申请日：2005-07-19
申请人： Christopher Michael Abernathy , Jonathan James Dement , Ronald Hall , Albert James Van Norstrand
发明人： Christopher Michael Abernathy , Jonathan James Dement , Ronald Hall , Albert James Van Norstrand
IPC分类号： G06F9/00
CPC分类号： G06F9/3836 , G06F9/3855 , G06F9/3857 , G06F9/3863
摘要： A method, system and processor for improving the performance of an in-order processor. A processor may include an execution unit with an execution pipeline that includes a backup pipeline and a regular pipeline. The backup pipeline may store a copy of the instructions issued to the regular pipeline. The execution pipeline may include logic for allowing instructions to flow from the backup pipeline to the regular pipeline following the flushing of the instructions younger than the exception detected in the regular pipeline. By maintaining a backup copy of the instructions issued to the regular pipeline, instructions may not need to be flushed from separate execution pipelines and re-fetched. As a result, one may complete the results of the execution units to the architected state out of order thereby allowing the completion point to vary among the different execution pipelines.
摘要翻译：一种用于改善按顺序处理器的性能的方法，系统和处理器。处理器可以包括具有包括备用流水线和常规流水线的执行流水线的执行单元。备用管道可以存储发给正常管道的指令的副本。执行流水线可以包括逻辑，用于在刷新比正常流水线中检测到的异常之后的指令更新时允许指令从备用流水线流向正常流水线。通过维护发布到常规流水线的指令的备份副本，可能不需要从单独的执行流程中刷新指令并重新获取。结果，可以将执行单元的结果完成到设计状态，从而使完成点在不同执行流水线之间变化。

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