专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07361847B2 Capacitance laminate and printed circuit board apparatus and method 失效
标题翻译：电容层压板和印刷电路板装置及方法
公开(公告)号：US07361847B2
公开(公告)日：2008-04-22
申请号：US11323515
申请日：2005-12-30
申请人： Gregory J. Dunn , Jaroslaw A. Magera , Jovica Savic
发明人： Gregory J. Dunn , Jaroslaw A. Magera , Jovica Savic
IPC分类号： H05K1/16
CPC分类号： H05K1/162 , H05K3/429 , H05K3/4602 , H05K3/4652 , H05K2201/0175 , H05K2201/09309 , H05K2201/09509 , H05K2201/09536 , H05K2201/09718
摘要： A method is for fabricating an embedded capacitance printed circuit board assembly (400, 1100). The embedded capacitance printed circuit board assembly includes two embedded capacitance structures (110). Each capacitance structure (110) includes a crystallized dielectric oxide layer (115) sandwiched between an outer electrode layer (120) and an inner electrode layer (125) in which the two inner electrode layers are electrically connected together. A rivet via (1315) and a stacked via (1110) formed from a button via (910) and a stacked blind via (1111) may be used to electrically connect the two inner electrode layers together. A spindle via (525) may be formed through the inner and outer layers. The multi-layer printed circuit board may be formed from a capacitive laminate (100) that includes two capacitance structures.
摘要翻译：一种用于制造嵌入式电容印刷电路板组件（400,1100）的方法。嵌入式电容印刷电路板组件包括两个嵌入式电容结构（110）。每个电容结构（110）包括夹在两个内部电极层电连接在一起的外部电极层（120）和内部电极层（125）之间的结晶化电介质氧化物层（115）。可以使用铆钉通孔（1315）和由按钮通孔（910）和堆叠的通孔（1111）形成的堆叠通孔（1110）将两个内部电极层电连接在一起。主轴通孔（525）可以通过内层和外层形成。多层印刷电路板可以由包括两个电容结构的电容层压板（100）形成。

2. 发明授权

US07138068B2 Printed circuit patterned embedded capacitance layer 失效
公开(公告)号：US07138068B2
公开(公告)日：2006-11-21
申请号：US11084938
申请日：2005-03-21
申请人： Gregory J. Dunn , Robert T. Croswell , Jaroslaw A. Magera , Jovica Savic , Aroon V. Tungare
发明人： Gregory J. Dunn , Robert T. Croswell , Jaroslaw A. Magera , Jovica Savic , Aroon V. Tungare
IPC分类号： H01L21/302
CPC分类号： C23F1/40 , C23F1/02 , C23F1/32 , C23F1/34 , H05K1/162 , H05K3/0044 , H05K3/025 , H05K3/06 , H05K3/429 , H05K2201/0175 , H05K2201/0179 , H05K2201/09309 , H05K2201/09509 , H05K2203/025 , H05K2203/0746
摘要： A method is disclosed for fabricating a patterned embedded capacitance layer. The method includes fabricating (1305, 1310) a ceramic oxide layer (510) overlying a conductive metal layer (515) overlying a printed circuit substrate (505), perforating (1320) the ceramic oxide layer within a region (705), and removing (1325) the ceramic oxide layer and the conductive metal layer in the region by chemical etching of the conductive metal layer. The ceramic oxide layer may be less than 1 micron thick.

3. 发明申请

US20080092376A1 METHOD FOR FABRICATING A PRINTED CIRCUIT BOARD 失效
标题翻译：制作印刷电路板的方法
公开(公告)号：US20080092376A1
公开(公告)日：2008-04-24
申请号：US11552368
申请日：2006-10-24
申请人： Jaroslaw A. Magera , Gregory J. Dunn , Jovica Savic
发明人： Jaroslaw A. Magera , Gregory J. Dunn , Jovica Savic
IPC分类号： H01L21/00
CPC分类号： H05K3/20 , H05K1/167 , H05K3/06 , H05K3/205 , H05K3/244 , H05K2201/0361 , H05K2203/0376 , H05K2203/0384 , Y10T29/49117 , Y10T29/49126 , Y10T29/49128 , Y10T29/49144 , Y10T29/49155 , Y10T29/49156
摘要： Fabricating (100, 1300) a printed circuit board includes fabricating patterned conductive traces (305, 310, 1410, 1415) onto a foil, laminating the patterned conductive traces to a printed circuit board substrate (405, 1505) by pressing on the foil, such that the conductive traces are pressed into a dielectric layer of the printed circuit board, and removing the foil to expose a co-planar surface of conductive trace surfaces and dielectric surfaces. Removal may be done by peeling (125) and/or etching (130, 1315).
摘要翻译：制造（100,1300）印刷电路板包括在箔上制造图案化的导电迹线（305,310,1410,1415），通过压在箔上将图案化的导电迹线层压到印刷电路板衬底（405,1505）上，使得导电迹线被压入印刷电路板的电介质层，并且去除箔以暴露导电迹线表面和电介质表面的共面表面。可以通过剥离（125）和/或蚀刻（130,1315）进行去除。

4. 发明授权

US07451540B2 Method for fabricating a printed circuit board 失效
标题翻译：印刷电路板的制造方法
公开(公告)号：US07451540B2
公开(公告)日：2008-11-18
申请号：US11552368
申请日：2006-10-24
申请人： Jaroslaw A. Magera , Gregory J. Dunn , Jovica Savic
发明人： Jaroslaw A. Magera , Gregory J. Dunn , Jovica Savic
IPC分类号： H05K3/02 , B05D5/12
CPC分类号： H05K3/20 , H05K1/167 , H05K3/06 , H05K3/205 , H05K3/244 , H05K2201/0361 , H05K2203/0376 , H05K2203/0384 , Y10T29/49117 , Y10T29/49126 , Y10T29/49128 , Y10T29/49144 , Y10T29/49155 , Y10T29/49156
摘要： Fabricating (100, 1300) a printed circuit board includes fabricating patterned conductive traces (305, 310, 1410, 1415) onto a foil, laminating the patterned conductive traces to a printed circuit board substrate (405, 1505) by pressing on the foil, such that the conductive traces are pressed into a dielectric layer of the printed circuit board, and removing the foil to expose a co-planar surface of conductive trace surfaces and dielectric surfaces. Removal may be done by peeling (125) and/or etching (130, 1315).
摘要翻译：制造（100,1300）印刷电路板包括在箔上制造图案化的导电迹线（305,310,1410,1415），通过压在箔上将图案化的导电迹线层压到印刷电路板衬底（405,1505）上，使得导电迹线被压入印刷电路板的电介质层，并且去除箔以暴露导电迹线表面和电介质表面的共面表面。可以通过剥离（125）和/或蚀刻（130,1315）进行去除。

5. 发明授权

US07444727B2 Method for forming multi-layer embedded capacitors on a printed circuit board 失效
标题翻译：在印刷电路板上形成多层嵌入式电容器的方法
公开(公告)号：US07444727B2
公开(公告)日：2008-11-04
申请号：US11276688
申请日：2006-03-10
申请人： Jovica Savic , Remy J. Chelini , Gregory J. Dunn
发明人： Jovica Savic , Remy J. Chelini , Gregory J. Dunn
IPC分类号： H01G7/00 , H01L21/20
CPC分类号： H01G4/33 , H01G4/12 , H05K1/162 , H05K3/0044 , H05K2201/0175 , H05K2201/0187 , H05K2201/0195 , H05K2201/0209 , H05K2201/09509 , H05K2203/025 , Y10T29/417 , Y10T29/43 , Y10T29/435 , Y10T29/49128 , Y10T29/49155 , Y10T29/49165
摘要： A method for forming embedded capacitors on a printed circuit board is disclosed. The capacitor is formed on the printed circuit board by a depositing a first dielectric layer over one or more electrodes situated on the PCB. Another electrode is formed on top of the first dielectric layer and a second dielectric layer is deposited on top of that electrode. A third electrode is formed on top of the second dielectric layer. The two dielectric layers are abrasively delineated in a single step by a method such as sand blasting to define portions of the first and second dielectric layers to create a multilayer capacitive structure.
摘要翻译：公开了一种在印刷电路板上形成嵌入式电容器的方法。通过在位于PCB上的一个或多个电极上沉积第一介电层，在印刷电路板上形成电容器。另一电极形成在第一电介质层的顶部，并且第二电介质层沉积在该电极的顶部上。在第二电介质层的顶部形成第三电极。通过诸如喷砂的方法在单个步骤中擦拭两个电介质层，以限定第一和第二电介质层的部分以产生多层电容结构。

6. 发明授权

US07193838B2 Printed circuit dielectric foil and embedded capacitors 失效
标题翻译：印刷电路介质箔和嵌入式电容器
公开(公告)号：US07193838B2
公开(公告)日：2007-03-20
申请号：US10744695
申请日：2003-12-23
申请人： Gregory J. Dunn , Remy J. Chilini , Robert T. Croswell , Timothy B. Dean , Claudia V. Gamboa , Jovica Savic
发明人： Gregory J. Dunn , Remy J. Chilini , Robert T. Croswell , Timothy B. Dean , Claudia V. Gamboa , Jovica Savic
IPC分类号： H01G4/30
CPC分类号： H05K1/162 , H05K3/025 , H05K3/429 , H05K2201/0175 , H05K2201/0355 , H05K2201/09309 , H05K2201/09509 , H05K2201/09718
摘要： A dielectric circuit board foil (400, 600) includes a conductive metal foil layer (210, 660), a crystallized dielectric oxide layer (405, 655) disposed adjacent a first surface of the conductive metal foil layer, a lanthanum nickelate layer (414, 664) disposed on the crystallized dielectric oxide layer, and an electrode layer (415, 665) that is substantially made of one or more base metals disposed on the lanthanum nickelate layer. The foil (400, 600) may be adhered to a printed circuit board sub-structure (700) and used to economically fabricate a plurality of embedded capacitors, including isolated capacitors of large capacitive density (>1000 pf/mm2).
摘要翻译：电介质电路板箔（400,600）包括导电金属箔层（210,660），邻近导电金属箔层的第一表面设置的结晶介电氧化物层（405,655），镍酸镧层（414），664）和基本上由设置在镍酸镧层上的一种或多种贱金属制成的电极层（415,665）。箔（400,600）可以粘附到印刷电路板子结构（700）上，并用于经济地制造多个嵌入式电容器，包括具有大电容密度（> 1000pf / mm 2）的隔离电容器， / SUP>）。

7. 发明授权

US06232042B1 Method for manufacturing an integral thin-film metal resistor 失效
标题翻译：制造整体薄膜金属电阻的方法
公开(公告)号：US06232042B1
公开(公告)日：2001-05-15
申请号：US09111189
申请日：1998-07-07
申请人： Gregory J. Dunn , Jovica Savic , Allyson Beuhler
发明人： Gregory J. Dunn , Jovica Savic , Allyson Beuhler
IPC分类号： G03F700
CPC分类号： H05K1/167 , G03F7/00 , H01C17/07 , H05K3/0023 , H05K3/025 , H05K3/048 , H05K3/386 , H05K2201/0317 , H05K2201/09881 , H05K2203/0152 , H05K2203/1461
摘要： A method for manufacturing a microelectronic assembly to have a resistor, and particularly a metal resistive film, with desirable processing and dimensional characteristics. The method generally entails applying a photosensitive dielectric to a substrate to form a dielectric layer. The dielectric layer is photoimaged to polymerize a first portion of the dielectric layer on a first region of the substrate, leaving the remainder of the dielectric layer unpolymerized. An electrically resistive film is then applied to the dielectric layer, and the dielectric layer is developed to remove concurrently the unpolymerized portion thereof and the portion of the resistive film overlying the unpolymerized portion, so that a portion of the resistive film remains over the second portion to form the resistor. An alternative process order is to apply the resistive film prior to exposing the dielectric layer to radiation, and then exposing the dielectric layer through the resistive film. The resistive film is preferably a multilayer film that includes an electrically resistive layer, such as NiP, NiCr or another nickel-containing alloy, and a sacrificial backing such as a layer of copper.
摘要翻译：一种用于制造具有所需加工和尺寸特性的电阻器，特别是金属电阻膜的微电子组件的方法。该方法通常需要将光敏电介质施加到衬底以形成电介质层。介电层被光刻以在基板的第一区域上聚合电介质层的第一部分，留下介电层的其余部分未聚合。然后将电阻膜施加到电介质层，并且电介质层被显影以同时除去其未聚合部分和覆盖未聚合部分的电阻膜的部分，使得电阻膜的一部分保留在第二部分上以形成电阻器。替代的处理顺序是在将电介质层暴露于辐射之前施加电阻膜，然后将电介质层暴露于电阻膜。电阻膜优选为包含电阻层的多层膜，例如NiP，NiCr或其它含镍合金，以及牺牲衬底，例如铜层。

8. 发明申请

US20080244885A1 METHOD FOR FORMING A CAPACITOR HAVING A COPPER ELECTRODE AND A HIGH SURFACE AREA ALUMINUM INNER LAYER 有权
标题翻译：形成具有铜电极和高表面积铝内层的电容器的方法
公开(公告)号：US20080244885A1
公开(公告)日：2008-10-09
申请号：US11697477
申请日：2007-04-06
申请人： Gregory J. Dunn , Jovica Savic , Philip M. Lessner , Albert K. Harrington
发明人： Gregory J. Dunn , Jovica Savic , Philip M. Lessner , Albert K. Harrington
IPC分类号： H01G7/00
CPC分类号： H05K1/162 , H01G4/008 , H01G4/33 , H05K3/382 , H05K3/429 , H05K2201/0338 , H05K2201/0355 , H05K2201/09309 , H05K2201/09509 , H05K2201/09718 , H05K2203/0315 , H05K2203/1536 , Y10T29/43
摘要： High capacitance value capacitors are formed using bimetal foils of an aluminum layer attached to a copper layer. The copper side of a bimetallic copper/aluminum foil or a monometallic aluminum foil is temporarily protected using aluminum or other materials, to form a sandwich. The exposed aluminum is treated to increase the surface area of the aluminum by at least one order of magnitude, while not attacking any portion of the protected metal. When the sandwich is separated, the treated bimetal foil is formed into a capacitor, where the copper layer is one electrode of the capacitor and the treated aluminum layer is in intimate contact with a dielectric layer of the capacitor.
摘要翻译：使用连接到铜层的铝层的双金属箔形成高电容值电容器。双金属铜/铝箔或单金属铝箔的铜面用铝或其他材料暂时保护，形成三明治。处理暴露的铝以将铝的表面积增加至少一个数量级，同时不侵蚀受保护金属的任何部分。当三明治分离时，处理的双金属箔形成电容器，其中铜层是电容器的一个电极，并且经处理的铝层与电容器的电介质层紧密接触。

9. 发明授权

US07105913B2 Two-layer patterned resistor 失效
标题翻译：双层图案电阻
公开(公告)号：US07105913B2
公开(公告)日：2006-09-12
申请号：US10743589
申请日：2003-12-22
申请人： Gregory J. Dunn , Scott N. Carney , Jovica Savic
发明人： Gregory J. Dunn , Scott N. Carney , Jovica Savic
IPC分类号： H01L27/082
CPC分类号： H01C7/006 , H01C1/148 , H01C17/065 , H01L23/49822 , H01L2924/0002 , H01L2924/00
摘要： A technique for fabricating a patterned resistor on a substrate produces a patterned resistor (101, 801, 1001, 1324, 1374) including two conductive end terminations (110, 810, 1010) on the substrate, a pattern of first resistive material (120, 815, 1015) having a first width (125) and a first sheet resistance, and a pattern of second resistive material (205, 820, 1020) having a second width (210) and a second sheet resistance that at least partially overlies the pattern of first resistive material. One of the first and second sheet resistances is a low sheet resistance and the other of the first and second resistances is a high sheet resistance. A ratio of the high sheet resistance to the low sheet resistance is at least ten to one. The pattern having the higher sheet resistance is substantially wider than the pattern having the low sheet resistance. The patterned resistor can be precision trimmed 1225.
摘要翻译：用于在衬底上制造图案化电阻器的技术产生包括在衬底上的两个导电端接（110,810,1010）的图案化电阻器（101,801,1001,1324,1374），第一电阻材料（120，具有第一宽度（125）和第一薄层电阻的第二电阻材料（205,820,1020）的图案，以及具有至少部分地覆盖图案的第二宽度（210）和第二薄层电阻的图案的第一电阻材料。第一和第二薄层电阻之一是低的薄层电阻，第一和第二电阻中的另一个是高的薄层电阻。高薄层电阻与低薄层电阻的比例至少为10比1。具有较高薄层电阻的图案基本上比具有低薄层电阻的图案更宽。图案化电阻器可精密修整1225。

10. 发明授权

US07038571B2 Polymer thick film resistor, layout cell, and method 失效
标题翻译：聚合物厚膜电阻，布局电池和方法
公开(公告)号：US07038571B2
公开(公告)日：2006-05-02
申请号：US10448993
申请日：2003-05-30
申请人： Gregory J. Dunn , Jovica Savic , Remy J. Chelini
发明人： Gregory J. Dunn , Jovica Savic , Remy J. Chelini
IPC分类号： H01C1/012
CPC分类号： H01C17/065 , H01C7/005 , H05K1/0266 , H05K1/095 , H05K1/167 , H05K3/12 , H05K2201/09781 , H05K2203/1453
摘要： A printed circuit polymer thick film (PTF) resistor includes tolerance control material that substantially surrounds the resistor body and significantly improves the linearity of resistance vs. resistor length, and significantly reduces resistor-to-resistor and board-to-board fabrication variances. In one embodiment, the tolerance control material is the same metallic material as the printed circuit conductors, and is formed in two finger patterns on each side of the resistor body, each finger pattern connected to one terminal pad of the resistor. A layout cell is used for fabricating the PTF resistor. A method is used for fabricating the PTF resistor.
摘要翻译：印刷电路聚合物厚膜（PTF）电阻器包括基本上围绕电阻器体的公差控制材料，并且显着地提高了电阻与电阻器长度的线性度，并且显着降低了电阻器对电阻器和板对板制造方差。在一个实施例中，公差控制材料与印刷电路导体相同的金属材料，并且形成在电阻体两侧的两个指形图案中，每个指状图案连接到电阻器的一个端子焊盘。布线单元用于制造PTF电阻。一种制造PTF电阻的方法。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式