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1. 发明授权

US4126899A Junction field effect transistor random access memory 失效
标题翻译：结场效应晶体管随机存取存储器
公开(公告)号：US4126899A
公开(公告)日：1978-11-21
申请号：US814648
申请日：1977-07-11
申请人： Jan Lohstroh , Joannes J. M. Koomen , Roelof H. W. Salters , Cornelis M. Hart
发明人： Jan Lohstroh , Joannes J. M. Koomen , Roelof H. W. Salters , Cornelis M. Hart
IPC分类号： G11C11/405 , G11C11/34 , G11C11/39 , G11C11/412 , H01L21/331 , H01L27/07 , H01L27/10 , H01L27/108 , H01L29/73 , H01L29/808 , G11C11/40
CPC分类号： H01L27/10 , G11C11/34 , G11C11/39 , G11C11/412 , H01L27/0716 , H01L27/108 , H01L29/808
摘要： A random access memory (RAM) in which each memory cell includes a JFET having two gate electrodes selectable by means of a single word line and a single bit line. The JFETs have a common electrode formed from the substrate of a semiconductor body common to each of the memory cells, which serves as one of the main electrodes of each of the JFETs.
摘要翻译：一种随机存取存储器（RAM），其中每个存储器单元包括具有可通过单个字线和单个位线选择的两个栅电极的JFET。 JFET具有由用作每个JFET的主电极之一的每个存储单元共用的半导体主体的基板形成的公共电极。

2. 发明授权

US4126900A Random access junction field-effect floating gate transistor memory 失效
标题翻译：随机存取结场效应浮栅晶体管存储器
公开(公告)号：US4126900A
公开(公告)日：1978-11-21
申请号：US814643
申请日：1977-07-11
申请人： Joannes J. M. Koomen , Jan Lohstroh , Roelof H. W. Salters , Adrianus T. Van Zanten
发明人： Joannes J. M. Koomen , Jan Lohstroh , Roelof H. W. Salters , Adrianus T. Van Zanten
IPC分类号： H01L27/10 , G11C11/35 , G11C11/401 , G11C11/404 , H01L21/8247 , H01L27/108 , H01L29/788 , H01L29/792 , G11C11/40
CPC分类号： G11C11/404 , G11C11/35 , H01L27/108
摘要： JFET memory structures, in particular for RAM's with non-destructive reading-out of the charge state of a floating gate electrode in which the primary selection is realized by means of capacitive coupling with the floating gate electrode. The secondary selection takes place on one of the main electrodes of the JFET structures in which the other main electrode can be connected to the supply. By means of a second common gate electrode the pinch-off voltage of the channels can be adjusted so that the channels are non-conductive in the non-selected condition and a good detection of the information state is obtained in the selected condition.
摘要翻译： JFET存储器结构，特别是对于具有非破坏性读出浮栅电极的电荷状态的RAM，其中通过与浮栅电极的电容耦合来实现初级选择。二次选择发生在JFET结构的一个主电极上，其中另一个主电极可以连接到电源。通过第二公共栅电极，可以调节通道的截止电压，使得通道在未选择的状态下不导通，并且在所选择的条件下获得良好的信息状态检测。

3. 发明授权

US4393471A Memory cell arrangement for a static memory 失效
标题翻译：用于静态存储器的存储单元布置
公开(公告)号：US4393471A
公开(公告)日：1983-07-12
申请号：US205816
申请日：1980-11-10
申请人： Cornelis M. Hart , Jan Lohstroh
发明人： Cornelis M. Hart , Jan Lohstroh
IPC分类号： G11C11/411 , H01L27/102 , H03K3/286 , G11C11/40
CPC分类号： G11C11/4113 , G11C11/4116 , H01L27/1025 , H03K3/286
摘要： A memory cell for a static memory, in which the number of control lines is reduced to a maximum of three by the use of a diode in one collector circuit and the series connection of a diode and a resistor in the other collector circuit of an Eccles-Jordan flip-flop, which diodes have an exponential characteristic with an exponent smaller than that of conventional diodes.
摘要翻译：用于静态存储器的存储单元，其中通过在一个集电极电路中使用二极管将控制线的数量减少到最大值，并且在Eccles的另一个集电极电路中的二极管和电阻器的串联连接 -Jordan触发器，其二极管具有指数小于常规二极管的指数特性。

4. 发明授权

US4148054A Method of manufacturing a semiconductor device and device manufactured by using the method 失效
标题翻译：使用该方法制造半导体器件和器件的方法
公开(公告)号：US4148054A
公开(公告)日：1979-04-03
申请号：US894241
申请日：1978-04-07
申请人： Cornelis M. Hart , Jan Lohstroh
发明人： Cornelis M. Hart , Jan Lohstroh
IPC分类号： H01L21/033 , H01L21/225 , H01L21/331 , H01L21/76 , H01L21/762 , H01L21/8226 , H01L21/8228 , H01L27/082 , H01L29/73 , H01L29/732 , H01L21/26
CPC分类号： H01L21/82285 , H01L21/033 , H01L21/2257 , H01L21/76202 , H01L21/76221 , H01L21/76224 , H01L27/0821 , H01L27/0826 , H01L29/7325 , Y10S148/111 , Y10S148/122
摘要： A method of manufacturing a semiconductor device, in particular a monolithic integrated circuit having very small complementary transistors. According to the invention two surface zones are provided beside each other without a masking tolerance of which one is formed by diffusion from a thin silicon layer. The distance between the surface zones is determined by the width of an oxide strip formed on the surface and on the edge of the silicon layer. The oxide strip is obtained by an underetching process and by using a silicon nitride mask deposited with shadow effect.
摘要翻译：一种制造半导体器件的方法，特别是具有非常小的互补晶体管的单片集成电路。根据本发明，两个表面区域彼此相邻设置，而不具有通过从薄硅层扩散形成的掩模公差。表面区域之间的距离由形成在表面上和硅层的边缘上的氧化物条的宽度确定。氧化物条是通过不定形的工艺和通过使用沉积有阴影效应的氮化硅掩模获得的。

5. 发明授权

US4322821A Memory cell for a static memory and static memory comprising such a cell 失效
标题翻译：用于静态存储器的存储单元和包含这样的单元的静态存储器
公开(公告)号：US4322821A
公开(公告)日：1982-03-30
申请号：US105357
申请日：1979-12-19
申请人： Jan Lohstroh , Cornelis M. Hart
发明人： Jan Lohstroh , Cornelis M. Hart
IPC分类号： G11C11/411 , H01L21/822 , H01L21/8229 , H01L27/04 , H01L27/102 , G11C11/40
CPC分类号： H01L27/1025 , G11C11/4116
摘要： A memory cell for integration into a static memory includes two transistors with cross-coupled base and collector regions. The collector regions are connected to p-n junction diode load elements having at least one region of polycrystalline silicon material. The collector regions of the transistors are connected to the regions of the diodes which are of the same conductivity type as the collector regions.
摘要翻译：用于集成到静态存储器中的存储单元包括具有交叉耦合基极和集电极区域的两个晶体管。集电极区域连接到具有至少一个多晶硅材料区域的p-n结二极管负载元件。晶体管的集电极区域连接到与集电极区域具有相同导电类型的二极管的区域。

6. 发明授权

US4245233A Photosensitive device arrangement using a drift field charge transfer mechanism 失效
标题翻译：使用漂移场电荷转移机构的感光器件布置
公开(公告)号：US4245233A
公开(公告)日：1981-01-13
申请号：US12164
申请日：1979-02-14
申请人： Jan Lohstroh
发明人： Jan Lohstroh
IPC分类号： G11C13/06 , H01L27/144 , H01L31/113 , H03K3/42 , G11C19/28 , H01L27/14 , H01L29/78
CPC分类号： G11C13/06 , H01L27/1443 , H01L31/1133
摘要： A photosensitive element and a photosensitive device arrangement using the element include a charge transfer structure having an electrode layer extending over a photosensitive area of a semiconductor body. In operation, a bias potential is applied to the electrode layer to form a depletion layer in the underlying body portion, and a drift field is produced in the depletion layer which extends in the direction of an edge portion of the electrode layer to permit photogenerated charge carriers to be transmitted towards the edge portion. A preferred structure for producing the desired drift field includes a resistive electrode having first and second connections for applying a potential difference along the resistive electrode. The photosensitive device arrangement further includes a localized charge-storage zone adjacent the edge portion of the electrode layer for collecting the photogenerated charge carriers and a detector circuit for measuring the charge state of the charge-storage zone.
摘要翻译：使用该元件的感光元件和感光器件布置包括具有在半导体本体的感光区域上延伸的电极层的电荷转移结构。在操作中，将偏置电位施加到电极层，以在下面的主体部分中形成耗尽层，并且在沿着电极层的边缘部分的方向延伸的耗尽层中产生漂移场，以允许光生电荷载体朝向边缘部分传输。用于产生所需漂移场的优选结构包括具有用于沿着电阻电极施加电位差的第一和第二连接的电阻电极。感光装置布置还包括与电极层的边缘部分相邻的用于收集光生电荷载流子的局部电荷储存区和用于测量电荷储存区的电荷状态的检测器电路。

7. 发明授权

US4577123A Integrated logic circuit having collector node with pull-up and clamp 失效
标题翻译：集成逻辑电路具有上拉和钳位的收集器节点
公开(公告)号：US4577123A
公开(公告)日：1986-03-18
申请号：US502866
申请日：1983-06-09
申请人： Johannes D. P. Van Den Crommenacker , Jan Lohstroh
发明人： Johannes D. P. Van Den Crommenacker , Jan Lohstroh
IPC分类号： H01L27/082 , H01L21/76 , H01L21/8226 , H01L27/02 , H01L27/07 , H03K19/013 , H03K19/091 , H01L29/70 , H03K5/08
CPC分类号： H01L27/0237 , H01L27/0755 , H03K19/013 , H03K19/0915
摘要： A logic circuit of the I.sup.2 L, the ISL or the STL type having a signal input formed by the control electrode of an inverter transistor and plural signal outputs each coupled through a diode to a main electrode of the inverter transistor, this main electrode being connected to a supply line through a pull-up connection. The improvement relates to a further connection path comprising a Schottky diode and a resistor which bridges the main current path of the inverter transistor and which reduces the voltage swing at the main electrode.
摘要翻译：具有由逆变器晶体管的控制电极形成的信号输入的I2L，ISL或STL型的逻辑电路，以及通过二极管耦合到反相晶体管的主电极的多个信号输出，该主电极连接到通过上拉连接的供电线。该改进涉及另外的连接路径，该连接路径包括肖特基二极管和电阻器，桥接反相晶体管的主电流路径并且降低主电极的电压摆幅。

8. 发明授权

US4399450A ROM With poly-Si to mono-Si diodes 失效
标题翻译： ROM具有多晶硅到单硅二极管
公开(公告)号：US4399450A
公开(公告)日：1983-08-16
申请号：US219059
申请日：1980-12-22
申请人： Jan Lohstroh
发明人： Jan Lohstroh
IPC分类号： G11C17/06 , G11C17/16 , H01L21/8229 , H01L23/52 , H01L27/10 , H01L27/102 , H01L29/04 , H01L27/04
CPC分类号： H01L27/1021 , G11C17/06 , G11C17/16 , H01L23/52 , H01L29/04 , H01L2924/0002 , Y10S257/91 , Y10S257/926
摘要： In a diode matrix of a permanent memory (ROM) the word line and bit line system is formed by a system of strip-shaped zones of one conductivity type provided in the silicon body and in the another system is formed by polycrystalline silicon tracks of the opposite conductivity type provided on the surface and forming mono-poly p-n junctions with the strip-shaped zones. High packing density and high speed are obtained.
摘要翻译：在永久存储器（ROM）的二极管矩阵中，字线和位线系统由设置在硅体中的一种导电类型的带状区域系统形成，而另一系统由多晶硅轨道形成在表面上提供相反的导电类型，并形成与带状区域的单聚点pn结。获得高填充密度和高速度。

9. 发明授权

US4019197A Semiconductor floating gate storage device with lateral electrode system 失效
标题翻译：具有横向电极系统的半导体浮动栅极存储装置
公开(公告)号：US4019197A
公开(公告)日：1977-04-19
申请号：US637705
申请日：1975-12-04
申请人： Jan Lohstroh , Roelof Herman Willem Salters
发明人： Jan Lohstroh , Roelof Herman Willem Salters
IPC分类号： G11C17/00 , G11C11/35 , G11C16/04 , H01L21/8247 , H01L29/788 , H01L29/792 , H01L29/78 , H01L29/04 , H01L29/34 , H01L29/88
CPC分类号： H01L29/7883 , G11C11/35
摘要： A semiconductor storage device having a field-effect transistor with a floating insulating gate electrode on which information-containing charge can be stored by tunneling charge carriers between the semiconductor body and the gate electrode. According to the invention the recording and erasing voltage is applied between two juxtaposed surface zones of the same conductivity type present outside the channel region and the source and drain zones, one of the surface zones, which is preferably also the source or drain zone, being separated from the floating gate electrode by an insulating layer having a thickness of less than 0.01 micron through which charge carriers can tunnel. Recording and erasing can be carried out at low voltages and with a voltage source of the same polarity relative to a reference potential.
摘要翻译：一种半导体存储装置，其具有具有浮动绝缘栅电极的场效应晶体管，通过在半导体本体和栅电极之间隧穿电荷载流子，可在其上存储含信息的电荷。根据本发明，记录和擦除电压施加在存在于沟道区域外部的相同导电类型的两个并置的表面区域和源极和漏极区域之间，优选地也是源极或漏极区域的一个表面区域是通过具有小于0.01微米的厚度的绝缘层与浮栅电极分离，电荷载体可穿过该绝缘层。记录和擦除可以在低电压下和相对于参考电位具有相同极性的电压源进行。

10. 发明授权

US4595942A Integrated circuit 失效
标题翻译：集成电路
公开(公告)号：US4595942A
公开(公告)日：1986-06-17
申请号：US934955
申请日：1978-08-18
申请人： Jan Lohstroh
发明人： Jan Lohstroh
IPC分类号： H01L21/74 , H01L21/8222 , H01L21/8226 , H01L27/02 , H01L27/07 , H01L27/082 , H03K19/091 , H01L27/04
CPC分类号： H01L27/0233 , H01L27/075 , H01L27/0821 , H01L27/0826
摘要： A compact integrated logic circuit having an inverter transistor and several coupling diodes adjoining the collector region of said transistor. Current is applied to the base of the transistor which forms the signal input. The inverter transistor has additional means by which an effective complementary auxiliary transistor is incorporated which dissipates a considerable part of the base current in the case the inverter transistor is overdriven so that the charge storage in the inverter transistor is restricted and controlled and by which a Schottky clamp diode across the base-collector junction of the inverter transistor can be avoided.
摘要翻译：一种紧凑的集成逻辑电路，具有逆变器晶体管和邻接所述晶体管的集电极区域的几个耦合二极管。电流被施加到形成信号输入的晶体管的基极。逆变器晶体管具有额外的装置，通过该装置，在逆变器晶体管过驱动的情况下，并入有效的互补辅助晶体管，其消耗相当大的基极电流，使得逆变器晶体管中的电荷存储受到限制和控制，并且通过该方式，肖特基可以避免跨越逆变器晶体管的基极 - 集电极结的二极管钳位二极管。

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