专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07380191B2 ABIST data compression and serialization for memory built-in self test of SRAM with redundancy 失效
标题翻译： ABIST数据压缩和串行化用于内存具有冗余的SRAM自检
公开(公告)号：US07380191B2
公开(公告)日：2008-05-27
申请号：US11054566
申请日：2005-02-09
申请人： James W. Dawson , Thomas J. Knips , Donald W. Plass , Kenneth J. Reyer
发明人： James W. Dawson , Thomas J. Knips , Donald W. Plass , Kenneth J. Reyer
IPC分类号： G01R31/28 , G01C29/00
CPC分类号： G11C29/1201 , G11C11/41 , G11C29/40 , G11C29/48 , G11C29/802 , G11C2029/3602
摘要： A method and apparatus for implementing ABIST data compression and serialization for memory built-in self test of SRAM with redundancy. The method includes providing detection signals asserted for one failing data out, two failing data outs, and greater than two failing data outs. The method also includes individually encoding the failing bit position of each corresponding failing data out with a binary representation value corresponding therewith. The method further includes serializing results of the providing detection signals and the individually encoding, and transmitting results of the serializing to a redundancy support register function on a single fail buss.
摘要翻译：一种实现ABIST数据压缩和串行化的方法和装置，用于具有冗余的SRAM的内存自检。该方法包括提供为一个故障数据输出断言的检测信号，两个故障数据输出和大于两个故障数据输出。该方法还包括用对应的二进制表示值来单独编码每个相应的故障数据输出的故障位位置。该方法还包括串行化提供检测信号和单独编码的结果，并将序列化的结果发送到单个故障总线上的冗余支持寄存器功能。

2. 发明授权

US07099206B2 High density bitline selection apparatus for semiconductor memory devices 失效
公开(公告)号：US07099206B2
公开(公告)日：2006-08-29
申请号：US11046101
申请日：2005-01-28
申请人： James W. Dawson , Donald W. Plass , Kenneth J. Reyer
发明人： James W. Dawson , Donald W. Plass , Kenneth J. Reyer
IPC分类号： G11C7/00
CPC分类号： G11C11/417 , G11C7/12 , G11C7/18 , G11C8/10 , G11C2207/002
摘要： A bitline selection apparatus for a semiconductor memory device includes a first local bitline pair and a second local bitline pair selectively coupled to a global bitline pair, each of the first and second local bitline pairs including a true bitline and a complementary bitline. Each of the true bitlines is selectively coupled to a common true node through an n-type pass device and a p-type pass device in parallel therewith, and each of the complementary bitlines is selectively coupled to a common complementary node through an n-type pass device and a p-type pass device in parallel therewith.

3. 发明授权

US07064990B1 Method and apparatus for implementing multiple column redundancy for memory 有权
标题翻译：用于为存储器实现多列冗余的方法和装置
公开(公告)号：US07064990B1
公开(公告)日：2006-06-20
申请号：US11053812
申请日：2005-02-09
申请人： James W. Dawson , Thomas J. Knips , Donald W. Plass , Kenneth J. Reyer
发明人： James W. Dawson , Thomas J. Knips , Donald W. Plass , Kenneth J. Reyer
IPC分类号： G11C7/00
CPC分类号： G11C29/848
摘要： An apparatus for implementing multiple memory column redundancy within an individual memory array includes a plurality of memory array elements internally partitioned into at least a pair of subcolumn elements. At least one spare memory element is configured at a size corresponding to one of the subcolumn elements. An input redundancy multiplexing stage and an output redundancy multiplexing stage are configured for steering around one or more defective memory array elements, and an input bit decoding stage and an output bit decoding stage are configured for implementing an additional, external multiplexing stage with respect to the input redundancy multiplexing stage and the output redundancy multiplexing stage.
摘要翻译：用于在单个存储器阵列内实现多个存储器列冗余的装置包括内部划分为至少一对子列元素的多个存储器阵列元件。至少一个备用存储器元件被配置为与子列元素之一对应的大小。配置输入冗余多路复用级和输出冗余多路复用级用于围绕一个或多个有缺陷的存储器阵列元件转向，并且输入位解码级和输出位解码级用于实现相对于输入冗余复用级和输出冗余复用级。

4. 发明授权

US07176725B2 Fast pulse powered NOR decode apparatus for semiconductor devices 失效
标题翻译：用于半导体器件的快速脉冲供电NOR解码装置
公开(公告)号：US07176725B2
公开(公告)日：2007-02-13
申请号：US11050895
申请日：2005-02-04
申请人： James W. Dawson , Donald W. Plass , Kenneth J. Reyer
发明人： James W. Dawson , Donald W. Plass , Kenneth J. Reyer
IPC分类号： H03K19/094 , H03K19/096
CPC分类号： H03K19/0963
摘要： A decoder circuit includes a pulse powered stage having a plurality of fan-in inputs thereto, a dynamic stage fed by the pulse powered stage, and a replica node selectively coupled to an output node of the pulse powered stage by a pass device. The pass device and the dynamic stage are controlled by a clock signal so as to enable a self-timed evaluation of the pulse-powered stage with a clocked enablement of the dynamic stage.
摘要翻译：解码器电路包括具有多个扇入输入的脉冲供电级，由脉冲供电级馈送的动态级，以及通过传递器件选择性地耦合到脉冲供电级的输出节点的复制节点。通过装置和动态级由时钟信号控制，以便能够利用动态级的时钟启用来对脉冲级的自定时评估。

5. 发明授权

US07299374B2 Clock control method and apparatus for a memory array 有权
标题翻译：用于存储器阵列的时钟控制方法和装置
公开(公告)号：US07299374B2
公开(公告)日：2007-11-20
申请号：US11050580
申请日：2005-02-03
申请人： James W. Dawson , Paul A. Bunce , Donald W. Plass , Kenneth J. Reyer
发明人： James W. Dawson , Paul A. Bunce , Donald W. Plass , Kenneth J. Reyer
IPC分类号： G06F1/08 , G06F1/04
CPC分类号： G06F1/04 , G11C7/22 , G11C7/222 , G11C7/227
摘要： A clock control method and apparatus are provided employing a clock control circuit which generates an array clock for a memory array from a system clock and a reset control signal. The reset control signal is one of a plurality of input control signals to the clock control circuit. When the system clock is below a predefined frequency threshold, the reset control signal is an array tracking reset signal, wherein the active pulse width of the array clock is system clock frequency independent, and when the system clock is above the predefined frequency threshold, the reset control signal is a mid-cycle reset signal, meaning that the active pulse width of the array clock is system clock frequency dependent. A bypass signal is provided as a third input control signal, which when active causes the clock control circuit to output an array clock which mirrors the system clock.
摘要翻译：提供了一种时钟控制方法和装置，其采用从系统时钟和复位控制信号产生用于存储器阵列的阵列时钟的时钟控制电路。复位控制信号是到时钟控制电路的多个输入控制信号之一。当系统时钟低于预定频率阈值时，复位控制信号是阵列跟踪复位信号，其中阵列时钟的有效脉冲宽度是系统时钟频率无关的，当系统时钟高于预定频率阈值时，复位控制信号是中周期复位信号，意味着阵列时钟的有效脉冲宽度取决于系统时钟。提供旁路信号作为第三输入控制信号，当有效时，时钟控制电路输出反映系统时钟的阵列时钟。

6. 发明授权

US07068554B1 Apparatus and method for implementing multiple memory redundancy with delay tracking clock 失效
标题翻译：用延迟跟踪时钟实现多重存储冗余的装置和方法
公开(公告)号：US07068554B1
公开(公告)日：2006-06-27
申请号：US11054272
申请日：2005-02-09
申请人： James W. Dawson , Thomas J. Knips , Donald W. Plass , Kenneth J. Reyer
发明人： James W. Dawson , Thomas J. Knips , Donald W. Plass , Kenneth J. Reyer
IPC分类号： G11C7/00
CPC分类号： G11C29/842
摘要： A memory redundancy control apparatus includes a static compare stage configured to compare bits of a requested memory address to corresponding fuse information bits representing a defective memory address. A dynamic stage is configured to receive outputs of the static compare stage, with an output of the dynamic stage being precharged so as to initially deactivate primary subarray decoding circuitry. The dynamic stage is further triggered by a clock signal thereto. Upon activation of the clock signal, the output of the dynamic stage remains precharged whenever a match exists between the requested memory address and the defective memory address, and the output of the dynamic stage is discharged whenever a mismatch exists between the requested memory address and the defective memory address. A delay tracking clock generator is configured to generate a delay tracking clock signal with respect to the dynamic stage, to gate the output of the dynamic stage to spare subarray decoding circuitry, wherein the spare subarray decoding circuitry is activated whenever the output of the dynamic stage remains precharged following activation of the clock signal.
摘要翻译：存储器冗余控制装置包括静态比较级，其被配置为将请求的存储器地址的比特与表示缺陷存储器地址的相应的熔丝信息比特进行比较。动态级被配置为接收静态比较级的输出，动态级的输出被预充电，以便最初去激活主子阵列解码电路。动态级由其时钟信号进一步触发。在激活时钟信号时，只要在请求的存储器地址和有缺陷的存储器地址之间存在匹配时，动态级的输出保持预充电，并且只要所请求的存储器地址和存储器地址之间存在不匹配，则动态级的输出被放电有缺陷的内存地址。延迟跟踪时钟发生器被配置为相对于动态级产生延迟跟踪时钟信号，以将动态级的输出门控到备用子阵列解码电路，其中每当动态级的输出被激活时，备用子阵列解码电路被激活在激活时钟信号后仍保持预充电。

7. 发明授权

US07170320B2 Fast pulse powered NOR decode apparatus with pulse stretching and redundancy steering 失效
标题翻译：具有脉冲拉伸和冗余转向功能的快速脉冲供电NOR解码装置
公开(公告)号：US07170320B2
公开(公告)日：2007-01-30
申请号：US11050933
申请日：2005-02-04
申请人： James W. Dawson , Thomas J. Knips , Donald W. Plass , Kenneth J. Reyer
发明人： James W. Dawson , Thomas J. Knips , Donald W. Plass , Kenneth J. Reyer
IPC分类号： H03K19/094 , H03K19/096
CPC分类号： H03K19/20
摘要： A decoder circuit includes a pulse powered stage having a plurality of fan-in inputs thereto, a dynamic stage fed by the pulse powered stage, and a replica node selectively coupled to an output node of the pulse powered stage by a pass device. The pass device and the dynamic stage are controlled by a clock signal so as to enable a self-timed evaluation of the pulse-powered stage with a clocked enablement of the dynamic stage. A pull up device restores the dynamic stage to a precharged condition, the pull up device controlled by a second clock signal independent of the first clock signal.
摘要翻译：解码器电路包括具有多个扇入输入的脉冲供电级，由脉冲供电级馈送的动态级，以及通过传递器件选择性地耦合到脉冲供电级的输出节点的复制节点。通过装置和动态级由时钟信号控制，以便能够利用动态级的时钟启用来对脉冲级的自定时评估。上拉装置将动态级恢复到预充电状态，上拉装置由与第一时钟信号无关的第二时钟信号控制。

8. 发明授权

US08937840B2 Digital voltage boost circuit 有权
标题翻译：数字升压电路
公开(公告)号：US08937840B2
公开(公告)日：2015-01-20
申请号：US13326727
申请日：2011-12-15
申请人： James W. Dawson , Noam Jungmann , Elazar Kachir , Udi Nir , Donald W. Plass
发明人： James W. Dawson , Noam Jungmann , Elazar Kachir , Udi Nir , Donald W. Plass
IPC分类号： G11C5/14
CPC分类号： G11C5/147
摘要： A digital voltage boost circuit, optionally working in parallel with an analog voltage regulator, periodically injects a constant amount of current each cycle into the bit line of a high density memory array to eliminate the bias voltage reduction which would otherwise occur. This results in a much faster recovery time and reduces the semiconductor real estate required. A pulse generator in the boost circuit generates one or more current modulation signals which control corresponding current supply devices in a current source. The boost circuit drives a constant amount of current to the bias voltage node each memory cycle.
摘要翻译：可选地与模拟电压调节器并联的数字升压电路周期性地将恒定量的电流每周期注入高密度存储器阵列的位线，以消除否则将发生的偏置电压降低。这导致恢复时间快得多，并减少了所需的半导体房地产。升压电路中的脉冲发生器产生一个或多个电流调制信号，其控制电流源中的相应的电流供应装置。升压电路驱动每个存储周期对偏置电压节点的恒定电流量。

9. 发明申请

US20130155787A1 Digital Voltage Boost Circuit 有权
标题翻译：数字电压升压电路
公开(公告)号：US20130155787A1
公开(公告)日：2013-06-20
申请号：US13326727
申请日：2011-12-15
申请人： James W. Dawson , Noam Jungmann , Elazar Kachir , Udi Nir , Donald W. Plass
发明人： James W. Dawson , Noam Jungmann , Elazar Kachir , Udi Nir , Donald W. Plass
IPC分类号： G11C5/14 , G05F3/02
CPC分类号： G11C5/147
摘要： A digital voltage boost circuit, optionally working in parallel with an analog voltage regulator, periodically injects a constant amount of current each cycle into the bit line of a high density memory array to eliminate the bias voltage reduction which would otherwise occur. This results in a much faster recovery time and reduces the semiconductor real estate required. A pulse generator in the boost circuit generates one or more current modulation signals which control corresponding current supply devices in a current source. The boost circuit drives a constant amount of current to the bias voltage node each memory cycle.
摘要翻译：可选地与模拟电压调节器并联的数字升压电路周期性地将恒定量的电流每周期注入高密度存储器阵列的位线，以消除否则将发生的偏置电压降低。这导致恢复时间快得多，并减少了所需的半导体房地产。升压电路中的脉冲发生器产生一个或多个电流调制信号，其控制电流源中的相应的电流供应装置。升压电路驱动每个存储周期对偏置电压节点的恒定电流量。

10. 发明授权

US06728912B2 SOI cell stability test method 失效
标题翻译： SOI电池稳定性试验方法
公开(公告)号：US06728912B2
公开(公告)日：2004-04-27
申请号：US09833724
申请日：2001-04-12
申请人： James W. Dawson , Paul A. Bunce , Donald W. Plass
发明人： James W. Dawson , Paul A. Bunce , Donald W. Plass
IPC分类号： G11C2900
CPC分类号： G11C29/12 , G11C8/08 , G11C29/34
摘要： A method for testing SOI technology memory circuits, such as in SRAMs, for weak SOI cells, uses a reset test circuit with a wordline pulse width control circuit which can be implemented without performance impact and allows using unused silicon to minimize area usage impact and permits screening of integrated SOI memory array circuits for weak SOI cells using the test reset circuit to selectively change the wordline pulse width to a reduced time while the memory cell bit select and write signals turn off at normal times to stress the cell write margin. Further, during test, the word line pulse width can be extended by blocking the reset signal of the reset path test circuit to the word path to produce a longer than normal pulse width. In addition, during a test for normal operations the reset signal is allowed to pass through a pass gate multiplexer of the reset test circuit.
摘要翻译：用于测试SOI技术存储器电路（例如SRAM）中用于弱SOI单元的方法使用具有字线脉冲宽度控制电路的复位测试电路，该电路可以在没有性能影响的情况下实现，并允许使用未使用的硅来最小化区域使用影响并允许使用测试复位电路筛选用于弱SOI单元的集成SOI存储器阵列电路，以便在正常时间存储单元位选择和写入信号关断以压缩单元写入裕度时选择性地将字线脉冲宽度改变为减小的时间。此外，在测试期间，可以通过将复位路径测试电路的复位信号阻塞到字路径来延长字线脉冲宽度，以产生比正常脉冲宽度更长的字线。此外，在正常操作的测试期间，允许复位信号通过复位测试电路的通过门极复用器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式