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1. 发明申请

US20090106538A1 System and Method for Implementing a Hardware-Supported Thread Assist Under Load Lookahead Mechanism for a Microprocessor 有权
标题翻译：用于在微处理器的负载前端机制下实现硬件支持的线程辅助的系统和方法
公开(公告)号：US20090106538A1
公开(公告)日：2009-04-23
申请号：US11877391
申请日：2007-10-23
申请人： James W. Bishop , Hung Q. Le , Dung Q. Nguyen , Wolfram Sauer , Benjamin W. Stolt , Michael T. Vaden
发明人： James W. Bishop , Hung Q. Le , Dung Q. Nguyen , Wolfram Sauer , Benjamin W. Stolt , Michael T. Vaden
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/383
摘要： The present invention includes a system and method for implementing a hardware-supported thread assist under load lookahead mechanism for a microprocessor. According to an embodiment of the present invention, hardware thread-assist mode can be activated when one thread of the microprocessor is in a sleep mode. When load lookahead mode is activated, the fixed point unit copies the content of one or more architected facilities from an active thread to corresponding architected facilities in the first inactive thread. The load-store unit performs at least one speculative load in load lookahead mode and writes the results of the at least one speculative load to a duplicated architected facility in the first inactive thread.
摘要翻译：本发明包括一种用于在微处理器的负载初始化机制下实现硬件支持的线程辅助的系统和方法。根据本发明的实施例，当微处理器的一个线程处于睡眠模式时，可以激活硬件线程辅助模式。当加载前瞻模式被激活时，固定点单元将一个或多个架构设施的内容从活动线程复制到第一个非活动线程中的相应的架构设施。加载存储单元在负载前瞻模式中执行至少一个推测负载，并将至少一个推测负载的结果写入第一非活动线程中的复制架构设施。

2. 发明授权

US07779234B2 System and method for implementing a hardware-supported thread assist under load lookahead mechanism for a microprocessor 有权
标题翻译：用于在微处理器的负载初始化机制下实现硬件支持的线程辅助的系统和方法
公开(公告)号：US07779234B2
公开(公告)日：2010-08-17
申请号：US11877391
申请日：2007-10-23
申请人： James W. Bishop , Hung Q. Le , Dung Q. Nguyen , Wolfram Sauer , Benjamin W. Stolt , Michael T. Vaden
发明人： James W. Bishop , Hung Q. Le , Dung Q. Nguyen , Wolfram Sauer , Benjamin W. Stolt , Michael T. Vaden
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/383
摘要： The present invention includes a system and method for implementing a hardware-supported thread assist under load lookahead mechanism for a microprocessor. According to an embodiment of the present invention, hardware thread-assist mode can be activated when one thread of the microprocessor is in a sleep mode. When load lookahead mode is activated, the fixed point unit copies the content of one or more architected facilities from an active thread to corresponding architected facilities in the first inactive thread. The load-store unit performs at least one speculative load in load lookahead mode and writes the results of the at least one speculative load to a duplicated architected facility in the first inactive thread.
摘要翻译：本发明包括一种用于在微处理器的负载初始化机制下实现硬件支持的线程辅助的系统和方法。根据本发明的实施例，当微处理器的一个线程处于睡眠模式时，可以激活硬件线程辅助模式。当加载前瞻模式被激活时，固定点单元将一个或多个架构设施的内容从活动线程复制到第一个非活动线程中的相应的架构设施。加载存储单元在负载前瞻模式中执行至少一个推测负载，并将至少一个推测负载的结果写入第一非活动线程中的复制架构设施。

3. 发明申请

US20080162517A1 METHOD AND SYSTEM FOR CREATING AN IN-MEMORY PHYSICAL DICTIONARY FOR DATA COMPRESSION 有权
公开(公告)号：US20080162517A1
公开(公告)日：2008-07-03
申请号：US11617610
申请日：2006-12-28
申请人： Balakrishna Raghavendra Iyer , Piotr M. Plachta , Wolfram Sauer , Steven W. White
发明人： Balakrishna Raghavendra Iyer , Piotr M. Plachta , Wolfram Sauer , Steven W. White
IPC分类号： G06F17/30
CPC分类号： H03M7/3088
摘要： Some aspects of the invention provide methods, systems, and computer program products for creating an in-memory physical dictionary for data compression. To that end, in accordance with aspects of the present invention, a new heuristic is defined for converting each of the plurality of logical nodes into a corresponding physical node forming a plurality of physical nodes; then place each of the physical nodes into the physical dictionary while traversing the dictionary tree in descending visit count order. Each physical node is placed in its nearest ascendant's cache-line with sufficient space. If there is no space in any of the ascendant's cache-line, then the physical node is placed into a new cache-line, unless a pre-defined packing threshold has been reached, in which case the physical node is placed in the first available cache-line.

4. 发明授权

US08037034B2 Methods of creating a dictionary for data compression 有权
标题翻译：创建数据压缩字典的方法
公开(公告)号：US08037034B2
公开(公告)日：2011-10-11
申请号：US11781833
申请日：2007-07-23
申请人： Piotr M. Plachta , Wolfram Sauer , Balakrishna Raghavendra Iyer , Steven Wayne White
发明人： Piotr M. Plachta , Wolfram Sauer , Balakrishna Raghavendra Iyer , Steven Wayne White
IPC分类号： G06F7/00 , G06F17/00
CPC分类号： H03M7/3088
摘要： Some aspects of the invention provide methods, systems, and computer program products for creating a static dictionary in which longer byte-strings are preferred. To that end, in accordance with aspects of the present invention, a new heuristic is defined to replace the aforementioned frequency count metric used to record the number of times a particular node in a data tree is visited. The new heuristic is based on counting the number of times an end-node of a particular byte-string is visited, while not incrementing a count for nodes storing characters in the middle of the byte-string as often as each time such nodes are visited. The result is an occurrence count metric that favors longer byte-strings, by being biased towards not incrementing the respective occurrence count values for nodes storing characters in the middle of a byte-string.
摘要翻译：本发明的一些方面提供用于创建静态词典的方法，系统和计算机程序产品，其中优选较长的字节串。为此，根据本发明的方面，定义新的启发式来代替用于记录数据树中的特定节点被访问次数的上述频率计数度量。新的启发式是基于对特定字节串的端节点进行访问的次数进行计数，而不会在每次访问这些节点时频繁地在字节串中间存储字符的节点递增计数。结果是有利于较长字节串的发生计数度量，偏向于不增加在字节串中间存储字符的节点的相应出现计数值。

5. 发明申请

US20080256345A1 Method and Apparatus for Conserving Power by Throttling Instruction Fetching When a Processor Encounters Low Confidence Branches in an Information Handling System 失效
标题翻译：当处理器在信息处理系统中遇到低置信度时通过调节指令获取来节省电力的方法和装置
公开(公告)号：US20080256345A1
公开(公告)日：2008-10-16
申请号：US11733589
申请日：2007-04-10
申请人： Pradip Bose , Alper Buyuktosunoglu , Chen-Yong Cher , Michael Karl Gschwind , Ravi Nair , Robert Alan Philhower , Wolfram Sauer , Raymond Cheung Yeung
发明人： Pradip Bose , Alper Buyuktosunoglu , Chen-Yong Cher , Michael Karl Gschwind , Ravi Nair , Robert Alan Philhower , Wolfram Sauer , Raymond Cheung Yeung
IPC分类号： G06F7/38
CPC分类号： G06F9/3844 , G06F1/3203 , G06F9/3802 , G06F9/3806
摘要： An information handling system includes a processor that throttles the instruction fetcher whenever the inaccuracy, or lack of confidence, in branch predictions for branch instructions stored in a branch instruction queue exceeds a predetermined threshold confidence level of inaccuracy or error. In this manner, fetch operations slow down to conserve processor power when it is likely that the processor will mispredict the outcome of branch instructions. Fetch operations return to full speed when it is likely that the processor will correctly predict the outcome of branch instructions.
摘要翻译：一种信息处理系统包括处理器，每当对分支指令队列中存储的分支指令的分支预测中的不准确性或缺乏置信度的不准确性或缺乏置信度超过预定的不准确度或误差的阈值置信水平时，可以节制指令获取器。以这种方式，当处理器可能会错误地预测分支指令的结果时，获取操作减慢以节省处理器功率。当处理器可能正确预测分支指令的结果时，获取操作将返回全速。

6. 发明申请

US20070229323A1 METHODS OF CREATING A DICTIONARY FOR DATA COMPRESSION 失效
标题翻译：创建数据压缩字典的方法
公开(公告)号：US20070229323A1
公开(公告)日：2007-10-04
申请号：US11278118
申请日：2006-03-30
申请人： Piotr Plachta , Wolfram Sauer , Balakrishna Iyer , Steven White
发明人： Piotr Plachta , Wolfram Sauer , Balakrishna Iyer , Steven White
IPC分类号： H03M7/34
CPC分类号： H03M7/3088
摘要： Some aspects of the invention provide methods, systems, and computer program products for creating a static dictionary in which longer byte-strings are preferred. To that end, in accordance with aspects of the present invention, a new heuristic is defined to replace the aforementioned frequency count metric used to record the number of times a particular node in a data tree is visited. The new heuristic is based on counting the number of times an end-node of a particular byte-string is visited, while not incrementing a count for nodes storing characters in the middle of the byte-string as often as each time such nodes are visited. The result is an occurrence count metric that favours longer byte-strings, by being biased towards not incrementing the respective occurrence count values for nodes storing characters in the middle of a byte-string.
摘要翻译：本发明的一些方面提供用于创建静态词典的方法，系统和计算机程序产品，其中优选较长的字节串。为此，根据本发明的方面，定义新的启发式来代替用于记录数据树中的特定节点被访问次数的上述频率计数度量。新的启发式是基于对特定字节串的端节点进行访问的次数进行计数，而不会在每次访问这些节点时频繁地在字节串中间存储字符的节点递增计数。结果是有利于较长字节串的发生计数度量，偏向于不增加在字节串中间存储字符的节点的相应出现计数值。

7. 发明申请

US20060174096A1 Methods and systems for storing branch information in an address table of a processor 失效
标题翻译：用于将分支信息存储在处理器的地址表中的方法和系统
公开(公告)号：US20060174096A1
公开(公告)日：2006-08-03
申请号：US11049014
申请日：2005-02-02
申请人： Brian Konigsburg , David Levitan , Wolfram Sauer , Samuel Thomas
发明人： Brian Konigsburg , David Levitan , Wolfram Sauer , Samuel Thomas
IPC分类号： G06F9/00
CPC分类号： G06F9/3806
摘要： Methods and systems for storing branch information in an address table of a processor are disclosed. A processor of the disclosed embodiments may generally include an instruction fetch unit connected to an instruction cache, a branch execution unit, and an address table being connected to the instruction fetch unit and the branch execution unit. The address table may generally be adapted to store a plurality of entries with each entry of the address table being adapted to store a base address and a base instruction tag. In a further embodiment, the branch execution unit may be adapted to determine the address of a branch instruction having an instruction tag based on the base address and the base instruction tag of an entry of the address table associated with the instruction tag. In some embodiments, the address table may further be adapted to store branch information.
摘要翻译：公开了将分支信息存储在处理器的地址表中的方法和系统。所公开的实施例的处理器通常可以包括连接到指令高速缓存的指令获取单元，分支执行单元和连接到指令获取单元和分支执行单元的地址表。地址表通常适于存储多个条目，其中地址表的每个条目适于存储基地址和基本指令标签。在另一实施例中，分支执行单元可以适于基于与指令标签相关联的地址表的条目的基地址和基本指令标签来确定具有指令标签的分支指令的地址。在一些实施例中，地址表还可以适于存储分支信息。

8. 发明授权

US07809933B2 System and method for optimizing branch logic for handling hard to predict indirect branches 有权
标题翻译：用于优化分支逻辑以处理难以预测间接分支的系统和方法
公开(公告)号：US07809933B2
公开(公告)日：2010-10-05
申请号：US11759350
申请日：2007-06-07
申请人： David S. Levitan , Wolfram Sauer
发明人： David S. Levitan , Wolfram Sauer
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/322 , G06F9/30181 , G06F9/3804
摘要： A system and method for optimizing the branch logic of a processor to improve handling of hard to predict indirect branches are provided. The system and method leverage the observation that there will generally be only one move to the count register (mtctr) instruction that will be executed while a branch on count register (bcctr) instruction has been fetched and not executed. With the mechanisms of the illustrative embodiments, fetch logic detects that it has encountered a bcctr instruction that is hard to predict and, in response to this detection, blocks the target fetch from entering the instruction buffer of the processor. At this point, the fetch logic has fetched all the instructions up to and including the bcctr instruction but no target instructions. When the next mtctr instruction is executed, the branch logic of the processor grabs the data and starts fetching using that target address. Since there are no other target instructions that were fetched, no flush is needed if that target address is the correct address, i.e. the branch prediction is correct.
摘要翻译：提供了一种用于优化处理器的分支逻辑以改善难以预测间接分支的处理的系统和方法。系统和方法利用这样的观察，通常只有一个移动到计数寄存器（mtctr）指令，在计数寄存器（bcctr）指令的分支已经被取出并且不被执行时将被执行。利用说明性实施例的机制，提取逻辑检测到它已经遇到难以预测的bcctr指令，并且响应于该检测阻止目标提取进入处理器的指令缓冲器。此时，提取逻辑已经获取了直到并包括bcctr指令但没有目标指令的所有指令。当执行下一个mtctr指令时，处理器的分支逻辑抓取数据，并使用该目标地址开始提取。由于没有其他目标指令被取出，如果目标地址是正确的地址，即分支预测是正确的，则不需要刷新。

9. 发明授权

US07454597B2 Computer processing system employing an instruction schedule cache 失效
标题翻译：计算机处理系统采用指令调度缓存
公开(公告)号：US07454597B2
公开(公告)日：2008-11-18
申请号：US11618948
申请日：2007-01-02
申请人： Krishnan K. Kailas , Ravi Nair , Sumedh W. Sathaye , Wolfram Sauer , John-David Wellman
发明人： Krishnan K. Kailas , Ravi Nair , Sumedh W. Sathaye , Wolfram Sauer , John-David Wellman
IPC分类号： G06F9/38
CPC分类号： G06F9/3836 , G06F9/3808 , G06F9/3838 , G06F9/384 , G06F9/3851 , G06F9/3855 , G06F9/3857
摘要： A processor core and method of executing instructions, both of which utilizes schedules, are presented. Each of the schedules includes a sequence of instructions, an address of a first of the instructions in the schedule, an order vector of an original order of the instructions in the schedule, a rename map of registers for each register in the schedule, and a list of register names used in the schedule. The schedule exploits instruction-level parallelism in executing out-of-order instructions. The processor core includes a schedule cache that is configured to store schedules, a shared cache configured to store both I-side and D-side cache data, and an execution resource for requesting a schedule to be executed from the schedule cache. The processor core further includes a scheduler disposed between the schedule cache and the cache. The scheduler creating the schedule using branch execution history from a branch history table to create the instructions when the schedule requested by the execution resource is not found in the schedule cache. The processor core executes the instructions according to the schedule being executed. The method includes requesting a schedule from a schedule cache. The method further includes fetching the schedule, when the schedule is found in the schedule cache; and creating the schedule, when the schedule is not found in the schedule cache. The method also includes renaming the registers in the schedule to avoid false dependencies in a processor core, mapping registers to renamed registers in the schedule, and stitching register values in and out of another schedule according to the list of register names and the rename map of registers.
摘要翻译：呈现执行指令的处理器核心和方法，两者都利用时间表。每个时间表包括指令序列，调度表中的第一指令的地址，调度表中的指令的原始顺序的顺序向量，调度表中每个寄存器的寄存器的重命名映射，以及时间表中使用的寄存器名称列表。该调度在执行无序指令时利用指令级并行性。处理器核心包括被配置为存储调度的调度高速缓存，被配置为存储I侧和D侧缓存数据的共享高速缓存以及用于从调度高速缓存请求执行调度的执行资源。处理器核心还包括设置在调度高速缓存和高速缓存之间的调度器。调度器使用分支执行历史从分支历史表创建调度，以便在调度高速缓存中找不到由执行资源请求的调度时创建指令。处理器核心根据执行的进度执行指令。该方法包括从调度缓存请求调度。该方法还包括当在调度高速缓存中找到调度时获取调度; 并且在调度缓存中找不到调度时创建调度。该方法还包括重新命名调度中的寄存器，以避免处理器核心中的错误依赖性，将寄存器映射到调度表中的重命名寄存器，以及根据寄存器名称和重命名映射列表将寄存器值拼接到另一个调度表中。注册

10. 发明授权

US07283072B1 Methods of creating a dictionary for data compression 失效
标题翻译：创建数据压缩字典的方法
公开(公告)号：US07283072B1
公开(公告)日：2007-10-16
申请号：US11278118
申请日：2006-03-30
申请人： Piotr M. Plachta , Wolfram Sauer , Balakrishna Raghavendra Iyer , Steven Wayne White
发明人： Piotr M. Plachta , Wolfram Sauer , Balakrishna Raghavendra Iyer , Steven Wayne White
IPC分类号： H03M7/00
CPC分类号： H03M7/3088
摘要： Some aspects of the invention provide methods, systems, and computer program products for creating a static dictionary in which longer byte-strings are preferred. To that end, in accordance with aspects of the present invention, a new heuristic is defined to replace the aforementioned frequency count metric used to record the number of times a particular node in a data tree is visited. The new heuristic is based on counting the number of times an end-node of a particular byte-string is visited, while not incrementing a count for nodes storing characters in the middle of the byte-string as often as each time such nodes are visited. The result is an occurrence count metric that favours longer byte-strings, by being biased towards not incrementing the respective occurrence count values for nodes storing characters in the middle of a byte-string.
摘要翻译：本发明的一些方面提供用于创建静态词典的方法，系统和计算机程序产品，其中优选较长的字节串。为此，根据本发明的方面，定义新的启发式来代替用于记录数据树中的特定节点被访问次数的上述频率计数度量。新的启发式是基于对特定字节串的端节点进行访问的次数进行计数，而不会在每次访问这些节点时频繁地在字节串中间存储字符的节点递增计数。结果是有利于较长字节串的发生计数度量，偏向于不增加在字节串中间存储字符的节点的相应出现计数值。

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