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1. 发明授权

US06660596B2 Double planar gated SOI MOSFET structure 失效
公开(公告)号：US06660596B2
公开(公告)日：2003-12-09
申请号：US10064318
申请日：2002-07-02
申请人： James W. Adkisson , John A. Bracchitta , John J. Ellis-Monaghan , Jerome B. Lasky , Effendi Leobandung , Kirk D. Peterson , Jed H. Rankin
发明人： James W. Adkisson , John A. Bracchitta , John J. Ellis-Monaghan , Jerome B. Lasky , Effendi Leobandung , Kirk D. Peterson , Jed H. Rankin
IPC分类号： H01L21336
CPC分类号： H01L29/785 , H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/66545 , H01L29/66795
摘要： A double gated silicon-on-insulator (SOI) MOSFET is fabricated by using a mandrel shallow trench isolation formation process, followed by a damascene gate. The double gated MOSFET features narrow diffusion lines defined sublithographically or lithographically and shrunk, damascene process defined by an STI-like mandrel process. The double gated SOI MOSFET increases current drive per layout width and provides low out conductance.

2. 发明授权

US06483156B1 Double planar gated SOI MOSFET structure 失效
标题翻译：双平面门控SOI MOSFET结构
公开(公告)号：US06483156B1
公开(公告)日：2002-11-19
申请号：US09526857
申请日：2000-03-16
申请人： James W. Adkisson , John A. Bracchitta , John J. Ellis-Monaghan , Jerome B. Lasky , Effendi Leobandung , Kirk D. Peterson , Jed H. Rankin
发明人： James W. Adkisson , John A. Bracchitta , John J. Ellis-Monaghan , Jerome B. Lasky , Effendi Leobandung , Kirk D. Peterson , Jed H. Rankin
IPC分类号： H01L2976
CPC分类号： H01L29/785 , H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/66545 , H01L29/66795
摘要： A double gated silicon-on-insulator (SOI) MOSFET is fabricated by using a mandrel shallow trench isolation formation process, followed by a damascene gate. The double gated MOSFET features narrow diffusion lines defined sublithographically or lithographically and shrunk, damascene process defined by an STI-like mandrel process. The double gated SOI MOSFET increases current drive per layout width and provides low out conductance.
摘要翻译：通过使用心轴浅沟槽隔离形成工艺制造双门控绝缘体上硅（SOI）MOSFET，随后是镶嵌栅极。双门控MOSFET具有狭窄的扩散线，其通过光刻或光刻和缩小限定，由STI样心轴工艺限定的镶嵌工艺。双门控SOI MOSFET增加每个布局宽度的电流驱动，并提供低导通电流。

3. 发明授权

US06197656B1 Method of forming planar isolation and substrate contacts in SIMOX-SOI. 失效
标题翻译：在SIMOX-SOI中形成平面隔离和衬底接触的方法。
公开(公告)号：US06197656B1
公开(公告)日：2001-03-06
申请号：US09047029
申请日：1998-03-24
申请人： James W. Adkisson , Jerome B. Lasky , Paul W. Pastel , Jed H. Rankin
发明人： James W. Adkisson , Jerome B. Lasky , Paul W. Pastel , Jed H. Rankin
IPC分类号： H01L21762
CPC分类号： H01L21/76264 , H01L21/76267
摘要： Oxygen implantation can be used to form a buried oxide layer in a substrate. A dielectric masking material is used to shape the buried oxide layer by changing the depth at which ions can implant based on the shape of the dielectric masking layer.
摘要翻译：可以使用氧气注入在衬底中形成掩埋氧化物层。介电掩模材料用于通过基于电介质掩模层的形状改变离子可以植入的深度来对掩埋氧化物层进行成形。

4. 发明授权

US6015745A Method for semiconductor fabrication 失效
标题翻译：半导体制造方法
公开(公告)号：US6015745A
公开(公告)日：2000-01-18
申请号：US80754
申请日：1998-05-18
申请人： James W. Adkisson , Jerome B. Lasky , Paul W. Pastel , Jed H. Rankin
发明人： James W. Adkisson , Jerome B. Lasky , Paul W. Pastel , Jed H. Rankin
IPC分类号： H01L21/76 , H01L21/762 , H01L27/12 , H01L29/786
CPC分类号： H01L21/76224 , H01L21/7624
摘要： An SOI semiconductor design methodology enables the implementation of simplified STI processes by the design and formation of a shallow trench isolation frame around an electrically active semiconductor region. The simplified STI processes include the fabrication of a trench by phase edge etching, trench sidewall oxidation, TEOS fill, and, finally a chemical or mechanical polish. The attribute which enables the simple process is that all isolation images can be current minimum or near minimum size, specifically no wider than twice the over-lay tolerance of the technology.
摘要翻译： SOI半导体设计方法通过在电活性半导体区域周围的浅沟槽隔离框架的设计和形成来实现简化的STI工艺。简化的STI工艺包括通过相边缘蚀刻，沟槽侧壁氧化，TEOS填充以及最终的化学或机械抛光来制造沟槽。实现简单过程的属性是所有隔离图像可以是当前最小或接近最小尺寸，特别是不超过技术的叠加公差的两倍。

5. 发明授权

US06300228B1 Multiple precipitation doping process 失效
标题翻译：多重沉淀掺杂工艺
公开(公告)号：US06300228B1
公开(公告)日：2001-10-09
申请号：US09386089
申请日：1999-08-30
申请人： James W. Adkisson , James A. Bruce , John J. Ellis-Monaghan , Randy W. Mann , Edward J. Nowak , Kirk D. Peterson
发明人： James W. Adkisson , James A. Bruce , John J. Ellis-Monaghan , Randy W. Mann , Edward J. Nowak , Kirk D. Peterson
IPC分类号： H01L2122
CPC分类号： H01L21/268 , H01L21/0455 , H01L21/2255
摘要： A multiple precipitation doping process for doping a semiconductor substrate (30) starts with forming an amorphous region (32) in the substrate (30). Through multiple laser exposures, multiple dopant precipitation films (52, 53) are formed on corresponding portions (34, 37) of the major surface (31) of the substrate (30) overlying the amorphous region (32). The substrate (30) is then annealed. The annealing process melts the amorphous region (32) and allows the dopants precipitated on the major surface (31) to diffuse into the substrate (30). The annealing process also crystallizes the semiconductor material the amorphous region (32). The substrate (30) becomes a single crystal semiconductor substrate with multiple doped regions (54, 57) therein. The depth of the doped regions (54, 57) is substantially equal to the depth of the amorphous region (32) before annealing.
摘要翻译：用于掺杂半导体衬底（30）的多次沉淀掺杂工艺从在衬底（30）中形成无定形区域（32）开始。通过多次激光曝光，在覆盖非晶区域（32）的衬底（30）的主表面（31）的相应部分（34,37）上形成多个掺杂剂沉淀膜（52,53）。然后将衬底（30）退火。退火过程熔化非晶区域（32）并且允许沉淀在主表面（31）上的掺杂剂扩散到衬底（30）中。退火过程也使非晶区域（32）半导体材料结晶。基板（30）成为具有多个掺杂区域（54,57）的单晶半导体基板。掺杂区域（54,57）的深度基本上等于退火前非晶区域（32）的深度。

6. 发明授权

US07303952B2 Method for fabricating doped polysilicon lines 有权
标题翻译：掺杂多晶硅生产线的制造方法
公开(公告)号：US07303952B2
公开(公告)日：2007-12-04
申请号：US10711771
申请日：2004-10-04
申请人： James W. Adkisson , John J. Ellis-Monaghan , Glenn C. MacDougall , Dale W. Martin , Kirk D. Peterson , Bruce W. Porth
发明人： James W. Adkisson , John J. Ellis-Monaghan , Glenn C. MacDougall , Dale W. Martin , Kirk D. Peterson , Bruce W. Porth
IPC分类号： H01L21/8238
CPC分类号： H01L21/265 , H01L21/28035 , H01L21/823842 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A method of fabricating polysilicon lines and polysilicon gates, the method of including: providing a substrate; forming a dielectric layer on a top surface of the substrate; forming a polysilicon layer on a top surface of the dielectric layer; implanting the polysilicon layer with N-dopant species, the N-dopant species about contained within the polysilicon layer; implanting the polysilicon layer with a nitrogen containing species, the nitrogen containing species essentially contained within the polysilicon layer.
摘要翻译：一种制造多晶硅线路和多晶硅栅极的方法，所述方法包括：提供衬底; 在所述基板的顶表面上形成介电层; 在所述电介质层的顶表面上形成多晶硅层; 用N掺杂物种注入多晶硅层，所述N掺杂物物质包含在所述多晶硅层内; 用含氮物质注入多晶硅层，含氮物质基本上包含在多晶硅层内。

7. 发明授权

US06858889B2 Polysilicon capacitor having large capacitance and low resistance 失效
标题翻译：具有大电容和低电阻的多晶硅电容器
公开(公告)号：US06858889B2
公开(公告)日：2005-02-22
申请号：US09878117
申请日：2001-06-08
申请人： James W. Adkisson , John A. Bracchitta , Jed H. Rankin , Anthony K. Stamper
发明人： James W. Adkisson , John A. Bracchitta , Jed H. Rankin , Anthony K. Stamper
IPC分类号： H01L21/02 , H01L21/314 , H01L21/334 , H01L21/8242 , H01L29/78 , H01L33/00
CPC分类号： H01L28/75 , H01L21/3144 , H01L28/91
摘要： A process for forming capacitors in a semiconductor device. In one embodiment, a first insulating layer is deposited on the semiconductor device; a trench is formed in the insulating layer; a first low resistance metal layer is formed covering the interior surface of the trench; a first polysilicon layer is formed over the first low resistance metal layer; a first dielectric layer is formed over the first polysilicon layer; a second polysilicon layer is formed over the first dielectric layer; a second low resistance metal layer is formed over the second polysilicon layer; a third polysilicon layer is formed over the second low resistance metal layer; a second dielectric layer is formed over the third polysilicon layer; a fourth polysilicon layer is formed over the second dielectric layer; a third low resistance metal layer is formed over the fourth polysilicon layer until the trench is filled; the semiconductor device is planarized until the first, second and third low resistance metal layers are exposed above the trench; finally, capacitor leads are formed to the first, second, and third low resistance metal layers.
摘要翻译：一种用于在半导体器件中形成电容器的工艺。在一个实施例中，第一绝缘层沉积在半导体器件上; 在绝缘层中形成沟槽; 形成覆盖沟槽内表面的第一低电阻金属层; 在第一低电阻金属层上形成第一多晶硅层; 第一介电层形成在第一多晶硅层上; 在第一介电层上形成第二多晶硅层; 在第二多晶硅层上形成第二低电阻金属层; 在第二低电阻金属层上形成第三多晶硅层; 在所述第三多晶硅层上形成第二电介质层; 在第二介电层上形成第四多晶硅层; 第四低电阻金属层形成在第四多晶硅层上，直到沟槽被填充; 半导体器件被平坦化，直到第一，第二和第三低电阻金属层暴露在沟槽上方; 最后，对第一，第二和第三低电阻金属层形成电容器引线。

8. 发明授权

US06261895B1 Polysilicon capacitor having large capacitance and low resistance and process for forming the capacitor 失效
标题翻译：具有大电容和低电阻的多晶硅电容器和用于形成电容器的工艺
公开(公告)号：US06261895B1
公开(公告)日：2001-07-17
申请号：US09225043
申请日：1999-01-04
申请人： James W. Adkisson , John A. Bracchitta , Jed H. Rankin , Anthony K. Stamper
发明人： James W. Adkisson , John A. Bracchitta , Jed H. Rankin , Anthony K. Stamper
IPC分类号： H01L218242
CPC分类号： H01L28/75 , H01L21/3144 , H01L28/91
摘要： A process for forming capacitors in a semiconductor device. In one embodiment, a first insulating layer is deposited on the semiconductor device; a trench is formed in the insulating layer; a first low resistance metal layer is formed covering the interior surface of the trench; a first polysilicon layer is formed over the first low resistance metal layer; a first dielectric layer is formed over the first polysilicon layer; a second polysilicon layer is formed over the first dielectric layer; a second low resistance metal layer is formed over the second polysilicon layer; a third polysilicon layer is formed over the second low resistance metal layer; a second dielectric layer is formed over the third polysilicon layer; a fourth polysilicon layer is formed over the second dielectric layer; a third low resistance metal layer is formed over the fourth polysilicon layer until the trench is filled; the semiconductor device is planarized until the first, second and third low resistance metal layers are exposed above the trench; finally, capacitor leads are formed to the first, second, and third low resistance metal layers.
摘要翻译：一种用于在半导体器件中形成电容器的工艺。在一个实施例中，第一绝缘层沉积在半导体器件上; 在绝缘层中形成沟槽; 形成覆盖沟槽内表面的第一低电阻金属层; 在第一低电阻金属层上形成第一多晶硅层; 第一介电层形成在第一多晶硅层上; 在第一介电层上形成第二多晶硅层; 在第二多晶硅层上形成第二低电阻金属层; 在第二低电阻金属层上形成第三多晶硅层; 在所述第三多晶硅层上形成第二电介质层; 在第二介电层上形成第四多晶硅层; 第四低电阻金属层形成在第四多晶硅层上，直到沟槽被填充; 半导体器件被平坦化，直到第一，第二和第三低电阻金属层暴露在沟槽上方; 最后，对第一，第二和第三低电阻金属层形成电容器引线。

9. 发明授权

US08716771B2 Anti-reflection structures for CMOS image sensors 有权
公开(公告)号：US08716771B2
公开(公告)日：2014-05-06
申请号：US13418706
申请日：2012-03-13
申请人： James W. Adkisson , John J. Ellis-Monaghan , Jeffrey P. Gambino , Charles F. Musante
发明人： James W. Adkisson , John J. Ellis-Monaghan , Jeffrey P. Gambino , Charles F. Musante
IPC分类号： H01L31/10 , H01L31/112
CPC分类号： H01L31/103 , H01L24/05 , H01L24/73 , H01L27/14603 , H01L27/1462 , H01L27/14627 , H01L27/14629 , H01L27/1464 , H01L27/14643 , H01L31/02165 , H01L31/0236 , H01L2224/04042 , H01L2224/05 , H01L2224/32225 , H01L2224/48227 , H01L2224/48464 , H01L2224/4847 , H01L2224/73265 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/0102 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01049 , H01L2924/01074 , H01L2924/12043 , H01L2924/14 , H01L2924/15311 , H01L2924/15312 , H01L2924/3025 , Y02E10/50 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： Optical structures having an array of protuberances between two layers having different refractive indices are provided. The array of protuberances has vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode of a CMOS image sensor. The array of protuberances provides high transmission of light with little reflection. The array of protuberances may be provided over a photodiode, in a back-end-of-line interconnect structure, over a lens for a photodiode, on a backside of a photodiode, or on a window of a chip package.

10. 发明授权

US08409904B2 Methods for forming anti-reflection structures for CMOS image sensors 有权
标题翻译： CMOS图像传感器形成抗反射结构的方法
公开(公告)号：US08409904B2
公开(公告)日：2013-04-02
申请号：US13165375
申请日：2011-06-21
申请人： James W. Adkisson , John J. Ellis-Monaghan , Jeffrey P. Gambino , Charles F. Musante
发明人： James W. Adkisson , John J. Ellis-Monaghan , Jeffrey P. Gambino , Charles F. Musante
IPC分类号： H01L21/00
CPC分类号： H01L27/14685 , H01L27/14618 , H01L27/14625 , H01L27/14627 , H01L27/14632 , H01L27/14645 , H01L27/14689 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/3025 , H01L2924/00014 , H01L2924/00
摘要： Protuberances, having vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode, are formed at an optical interface between two layers having different refractive indices. The protuberances may be formed by employing self-assembling block copolymers that form an array of sublithographic features of a first polymeric block component within a matrix of a second polymeric block component. The pattern of the polymeric block component is transferred into a first optical layer to form an array of nanoscale protuberances. Alternately, conventional lithography may be employed to form protuberances having dimensions less than the wavelength of light. A second optical layer is formed directly on the protuberances of the first optical layer. The interface between the first and second optical layers has a graded refractive index, and provides high transmission of light with little reflection.
摘要翻译：在具有不同折射率的两层之间的光学界面处形成具有小于由光电二极管可检测的光的波长范围的垂直和横向尺寸的突起。突起可以通过采用在第二聚合物嵌段组分的基质内形成第一聚合物嵌段组分的亚光刻特征阵列的自组装嵌段共聚物来形成。聚合物嵌段组分的图案被转移到第一光学层中以形成纳米级突起的阵列。或者，可以使用常规光刻来形成尺寸小于光的波长的突起。第二光学层直接形成在第一光学层的突起上。第一和第二光学层之间的界面具有渐变的折射率，并提供很少的反射光的高透射率。

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