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1. 发明授权

US07459360B2 Method of forming pixel sensor cell having reduced pinning layer barrier potential 有权
标题翻译：形成具有降低的钉扎层势垒势垒的像素传感器单元的方法
公开(公告)号：US07459360B2
公开(公告)日：2008-12-02
申请号：US11681454
申请日：2007-03-02
申请人： James W. Adkisson , Andres Bryant , John Ellis-Monaghan , Jeffrey P. Gambino , Mark D. Jaffe , Jerome B. Lasky , Richard A. Phelps
发明人： James W. Adkisson , Andres Bryant , John Ellis-Monaghan , Jeffrey P. Gambino , Mark D. Jaffe , Jerome B. Lasky , Richard A. Phelps
IPC分类号： H01L21/8238
CPC分类号： H01L27/14689 , H01L27/14603 , H01L27/14609 , H01L31/0352
摘要： A method of forming a pixel sensor cell structure. The method of forming the pixel cell comprises forming a doped layer adjacent to a first side of a transfer gate structure for coupling a collection well region and a channel region. Potential barrier interference to charge transfer caused by a pinning layer is reduced.
摘要翻译：一种形成像素传感器单元结构的方法。形成像素单元的方法包括形成与传输栅极结构的第一侧相邻的掺杂层，用于耦合收集阱区和沟道区。减少了由钉扎层引起的对电荷转移的电势障碍干扰。

2. 发明授权

US07205591B2 Pixel sensor cell having reduced pinning layer barrier potential and method thereof 有权
标题翻译：具有降低的钉扎层势垒势的像素传感器单元及其方法
公开(公告)号：US07205591B2
公开(公告)日：2007-04-17
申请号：US10907570
申请日：2005-04-06
申请人： James W. Adkisson , Andres Bryant , John Ellis-Monaghan , Jeffrey P. Gambino , Mark D. Jaffe , Jerome B Lasky , Richard A. Phelps
发明人： James W. Adkisson , Andres Bryant , John Ellis-Monaghan , Jeffrey P. Gambino , Mark D. Jaffe , Jerome B Lasky , Richard A. Phelps
IPC分类号： H01L27/148
CPC分类号： H01L27/14689 , H01L27/14603 , H01L27/14609 , H01L31/0352
摘要： A pixel sensor cell structure and method of manufacture. The pixel cell comprises a doped layer formed adjacent to a first side of a transfer gate structure for coupling a collection well region and a channel region. Potential barrier interference to charge transfer caused by a pinning layer is reduced.
摘要翻译：像素传感器单元结构及其制造方法。像素单元包括与传输栅极结构的第一侧相邻形成的用于耦合收集阱区和沟道区的掺杂层。减少了由钉扎层引起的对电荷转移的电势障碍干扰。

3. 发明授权

US07217968B2 Recessed gate for an image sensor 有权
标题翻译：嵌入式门用于图像传感器
公开(公告)号：US07217968B2
公开(公告)日：2007-05-15
申请号：US10905097
申请日：2004-12-15
申请人： James W. Adkisson , John Ellis-Monaghan , Mark D. Jaffe , Jerome B. Lasky
发明人： James W. Adkisson , John Ellis-Monaghan , Mark D. Jaffe , Jerome B. Lasky
IPC分类号： H01L31/062
CPC分类号： H01L27/14603 , H01L27/14601 , H01L27/14689 , H01L29/66621
摘要： A novel image sensor cell structure and method of manufacture. The imaging sensor comprises a substrate, a gate comprising a dielectric layer and gate conductor formed on the dielectric layer, a collection well layer of a first conductivity type formed below a surface of the substrate adjacent a first side of the gate conductor, a pinning layer of a second conductivity type formed atop the collection well at the substrate surface, and a diffusion region of a first conductivity type formed adjacent a second side of the gate conductor, the gate conductor forming a channel region between the collection well layer and the diffusion region. Part of the gate conductor bottom is recessed below the surface of the substrate. Preferably, a portion of the gate conductor is recessed at or below a bottom surface of the pinning layer to a depth such that the collection well intersects the channel region.
摘要翻译：一种新颖的图像传感器单元结构及其制造方法。成像传感器包括基板，包括电介质层和形成在电介质层上的栅极导体的栅极，形成在与栅极导体的第一侧相邻的基板的表面下面的第一导电类型的收集阱层，钉扎层在基板表面上形成在集合阱顶部的第二导电类型的第一导电类型的扩散区和在栅极导体的第二侧附近形成的第一导电类型的扩散区，栅极导体在集电阱层和扩散区之间形成沟道区。栅极导体底部的一部分凹陷在基板的表面下方。优选地，栅极导体的一部分在钉扎层的底表面处或下方凹陷到使得收集阱与沟道区相交的深度。

4. 发明授权

US07572701B2 Recessed gate for a CMOS image sensor 有权
标题翻译： CMOS图像传感器的嵌入式门
公开(公告)号：US07572701B2
公开(公告)日：2009-08-11
申请号：US11735223
申请日：2007-04-13
申请人： James W. Adkisson , John Ellis-Monaghan , Mark D. Jaffe , Jerome B. Lasky
发明人： James W. Adkisson , John Ellis-Monaghan , Mark D. Jaffe , Jerome B. Lasky
IPC分类号： H01L21/02 , H01L31/113
CPC分类号： H01L27/14603 , H01L27/14601 , H01L27/14689 , H01L29/66621
摘要： A novel CMOS image sensor cell structure and method of manufacture. The imaging sensor comprises a substrate having an upper surface, a gate comprising a dielectric layer formed on the substrate and a gate conductor formed on the gate dielectric layer, a collection well layer of a first conductivity type formed below a surface of the substrate adjacent a first side of the gate conductor, a pinning layer of a second conductivity type formed atop the collection well at the substrate surface, and a diffusion region of a first conductivity type formed adjacent a second side of the gate conductor, the gate conductor forming a channel region between the collection well layer and the diffusion region. A portion of the bottom of the gate conductor is recessed below the surface of the substrate. Preferably, a portion of the gate conductor is recessed at or below a bottom surface of the pinning layer to a depth such that the collection well intersects the channel region thereby eliminating any potential barrier interference caused by the pinning layer.
摘要翻译：一种新颖的CMOS图像传感器单元结构及其制造方法。成像传感器包括具有上表面的基板，包括形成在基板上的电介质层的栅极和形成在栅极电介质层上的栅极导体，形成在基板表面附近的第一导电类型的集合阱层栅极导体的第一侧，形成在基板表面上的集电阱顶部的第二导电类型的钉扎层，以及邻近栅极导体的第二侧形成的第一导电类型的扩散区域，栅极导体形成沟道收集阱层和扩散区域之间的区域。栅极导体的底部的一部分在衬底的表面下方凹进。优选地，栅极导体的一部分在钉扎层的底表面处或下方凹陷到深度，使得收集阱与沟道区相交，从而消除由钉扎层引起的任何潜在的屏障干扰。

5. 发明授权

US09543356B2 Pixel sensor cell including light shield 有权
标题翻译：像素传感器单元包括遮光罩
公开(公告)号：US09543356B2
公开(公告)日：2017-01-10
申请号：US12538194
申请日：2009-08-10
申请人： Jeffrey P. Gambino , Mark D. Jaffe , John Ellis-Monaghan , Richard Rassel
发明人： Jeffrey P. Gambino , Mark D. Jaffe , John Ellis-Monaghan , Richard Rassel
IPC分类号： H01L27/148 , H01L27/146
CPC分类号： H01L27/14689 , H01L27/14609 , H01L27/14623 , H01L27/1464
摘要： CMOS image sensor pixel sensor cells, methods for fabricating the pixel sensor cells and design structures for fabricating the pixel sensor cells are designed to allow for back side illumination in global shutter mode by providing light shielding from back side illumination of at least one transistor within the pixel sensor cells. In a first particular generalized embodiment, a light shielding layer is located and formed interposed between a first semiconductor layer that includes a photoactive region and a second semiconductor layer that includes the at least a second transistor, or a floating diffusion, that is shielded by the light blocking layer. In a second generalized embodiment, a thin film transistor and a metal-insulator-metal capacitor are used in place of a floating diffusion, and located shielded in a dielectric isolated metallization stack over a carrier substrate.
摘要翻译： CMOS图像传感器像素传感器单元，用于制造像素传感器单元的方法和用于制造像素传感器单元的设计结构被设计成允许在全局快门模式中进行背面照明，通过提供来自至少一个晶体管的背侧照明的光屏蔽像素传感器单元。在第一特定广义实施例中，遮光层位于包括光活性区的第一半导体层和包括至少第二晶体管的第二半导体层之间并形成，或者浮置扩散部被屏蔽遮光层。在第二广义实施例中，使用薄膜晶体管和金属 - 绝缘体 - 金属电容器来代替浮动扩散，并且被定位在载体衬底上的介电隔离金属化堆叠中。

6. 发明申请

US20100230729A1 PIXEL SENSOR CELL INCLUDING LIGHT SHIELD 有权
标题翻译：像素传感器细胞，包括光泽
公开(公告)号：US20100230729A1
公开(公告)日：2010-09-16
申请号：US12538194
申请日：2009-08-10
申请人： John Ellis-Monaghan , Jeffrey P. Gambino , Mark D. Jaffe , Richard J. Rassel
发明人： John Ellis-Monaghan , Jeffrey P. Gambino , Mark D. Jaffe , Richard J. Rassel
IPC分类号： H01L27/148 , H01L27/146 , H01L31/0216 , H01L21/30 , G06F17/50
CPC分类号： H01L27/14689 , H01L27/14609 , H01L27/14623 , H01L27/1464
摘要： CMOS image sensor pixel sensor cells, methods for fabricating the pixel sensor cells and design structures for fabricating the pixel sensor cells are designed to allow for back side illumination in global shutter mode by providing light shielding from back side illumination of at least one transistor within the pixel sensor cells. In a first particular generalized embodiment, a light shielding layer is located and formed interposed between a first semiconductor layer that includes a photoactive region and a second semiconductor layer that includes the at least a second transistor, or a floating diffusion, that is shielded by the light blocking layer. In a second generalized embodiment, a thin film transistor and a metal-insulator-metal capacitor are used in place of a floating diffusion, and located shielded in a dielectric isolated metallization stack over a carrier substrate
摘要翻译： CMOS图像传感器像素传感器单元，用于制造像素传感器单元的方法和用于制造像素传感器单元的设计结构被设计成允许在全局快门模式中进行背面照明，通过提供来自至少一个晶体管的背面照明的光屏蔽像素传感器单元。在第一特定广义实施例中，遮光层位于包括光活性区的第一半导体层和包括至少第二晶体管的第二半导体层之间并形成，或者浮置扩散部被屏蔽遮光层。在第二广义实施例中，使用薄膜晶体管和金属 - 绝缘体 - 金属电容器代替浮动扩散，并且被定位在载体衬底上的电介质隔离金属化堆叠中

7. 发明申请

US20130260183A1 THREE DIMENSIONAL SOLID-STATE BATTERY INTEGRATED WITH CMOS DEVICES 审中-公开
标题翻译：三维固态电池与CMOS器件集成
公开(公告)号：US20130260183A1
公开(公告)日：2013-10-03
申请号：US13432353
申请日：2012-03-28
申请人： John Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed Hickory Rankin
发明人： John Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed Hickory Rankin
IPC分类号： H01M2/00 , G06F19/00
CPC分类号： H01M10/425 , H01M2/22 , H01M2/26 , H01M4/0473 , H01M4/386 , H01M10/0525 , H01M10/0562 , H01M10/058 , H01M2220/30 , H01M2300/0068 , Y10T29/49108
摘要： A solid-state battery structure having a plurality of battery cells formed in a substrate. The plurality of battery cells includes a first current collector layer overlying a first insulating layer and a first electrode layer overlying the first current collector layer. The battery structure further includes a second current collector layer overlying a patterned second electrode layer. The patterned second electrode layer overlies the substrate and forms a plurality of sub-arrays of the battery cells. The battery structure further includes a second insulating layer overlying the second current collector layer. The second insulating layer substantially laterally surrounds first and second contact pads. The first pad is electrically connected to the first current collector layer and the second pad is electrically connected to the second current collector layer. The first and second contact pads are in electrical communication, through at least two electrical wires, with a circuit located upon the substrate.
摘要翻译：一种具有形成在基板中的多个电池单元的固态电池结构。多个电池单元包括覆盖第一绝缘层的第一集电器层和覆盖第一集电器层的第一电极层。电池结构还包括覆盖图案化的第二电极层的第二集电器层。图案化的第二电极层覆盖在衬底上并形成电池单元的多个子阵列。电池结构还包括覆盖第二集电器层的第二绝缘层。第二绝缘层基本上横向围绕第一和第二接触焊盘。第一焊盘电连接到第一集电器层，第二焊盘电连接到第二集电器层。第一和第二接触焊盘通过至少两根电线电连接，电路位于衬底上。

8. 发明申请

US20070296006A1 STRUCTURE FOR PIXEL SENSOR CELL THAT COLLECTS ELECTRONS AND HOLES 失效
标题翻译：用于收集电子和孔的像素传感器单元的结构
公开(公告)号：US20070296006A1
公开(公告)日：2007-12-27
申请号：US11850776
申请日：2007-09-06
申请人： James Adkisson , Andres Bryant , John Ellis-Monaghan , Mark Jaffe , Jeffrey Johnson , Alain Loiseau
发明人： James Adkisson , Andres Bryant , John Ellis-Monaghan , Mark Jaffe , Jeffrey Johnson , Alain Loiseau
IPC分类号： H01L31/00
CPC分类号： H01L27/14603 , H01L27/14609 , H01L27/14689 , H01L31/035281 , H01L31/1037
摘要： The present invention relates to a design structure for a pixel sensor cell. The pixel sensor cell approximately doubles the available signal for a given quanta of light. A design structure for a pixel sensor cell having reduced complexity includes an n-type collection well region formed beneath a surface of a substrate for collecting electrons generated by electromagnetic radiation impinging on the pixel sensor cell and a p-type collection well region formed beneath the surface of the substrate for collecting holes generated by the impinging photons. A circuit structure having a first input is coupled to the n-type collection well region and a second input is coupled to the p-type collection well region, wherein an output signal of the pixel sensor cell is the magnitude of the difference of a signal of the first input and a signal of the second input.
摘要翻译：本发明涉及一种像素传感器单元的设计结构。像素传感器单元对于给定的光量大约使可用信号加倍。具有降低的复杂度的像素传感器单元的设计结构包括形成在基板的表面下面的n型收集阱区域，用于收集电子辐射产生的电子撞击在像素传感器单元上，以及p型收集阱区域用于收集由撞击光子产生的孔的基板的表面。具有第一输入的电路结构耦合到n型收集阱区域，而第二输入端耦合到p型收集阱区域，其中像素传感器单元的输出信号是信号的差值的大小的第一输入和第二输入的信号。

9. 发明申请

US20070145438A1 PIXEL SENSOR CELL HAVING REDUCED PINNING LAYER BARRIER POTENTIAL AND METHOD THEREOF 有权
标题翻译：具有减少的钉扎层障碍物的像素传感器电池及其方法
公开(公告)号：US20070145438A1
公开(公告)日：2007-06-28
申请号：US11681454
申请日：2007-03-02
申请人： James Adkisson , Andres Bryant , John Ellis-Monaghan , Jeffrey Gambino , Mark Jaffe , Jerome Lasky , Richard Phelps
发明人： James Adkisson , Andres Bryant , John Ellis-Monaghan , Jeffrey Gambino , Mark Jaffe , Jerome Lasky , Richard Phelps
IPC分类号： H01L31/113
CPC分类号： H01L27/14689 , H01L27/14603 , H01L27/14609 , H01L31/0352
摘要： A pixel sensor cell structure and method of manufacture. The pixel cell comprises a doped layer formed adjacent to a first side of a transfer gate structure for coupling a collection well region and a channel region. Potential barrier interference to charge transfer caused by a pinning layer is reduced.
摘要翻译：像素传感器单元结构及其制造方法。像素单元包括与传输栅极结构的第一侧相邻形成的用于耦合收集阱区和沟道区的掺杂层。减少了由钉扎层引起的对电荷转移的电势障碍干扰。

10. 发明授权

US07977714B2 Wrapped gate junction field effect transistor 有权
标题翻译：封装栅结场效应晶体管
公开(公告)号：US07977714B2
公开(公告)日：2011-07-12
申请号：US11875190
申请日：2007-10-19
申请人： John Ellis-Monaghan , Richard A. Phelps , Robert M. Rassel , Steven H. Voldman , Michael J. Zierak
发明人： John Ellis-Monaghan , Richard A. Phelps , Robert M. Rassel , Steven H. Voldman , Michael J. Zierak
IPC分类号： H01L29/808 , H01L21/337
CPC分类号： H01L29/808 , H01L29/1058 , H01L29/1066 , H01L29/1608 , H01L29/20 , H01L29/22 , H01L29/66901 , H01L29/66924
摘要： A wrapped gate junction field effect transistor (JFET) with at least one semiconductor channel having a first conductivity type doping is provided. Both sidewalls of each of the at least one semiconductor channel laterally abuts a side gate region having a second conductivity type doping, which is the opposite of the first conductivity doping. Further, the at least one semiconductor channel vertically abuts a top gate region and at least one bottom gate region, both having the second conductivity type doping. The gate electrode, which comprises side gate region, the top gate region, and at least one bottom gate regions, wraps around each of the at least one semiconductor channel to provide tight control of the current, i.e., a low off-current, through the at least one semiconductor channel. By employing multiple channels, the JFET may provide a high on-current.
摘要翻译：提供具有至少一个具有第一导电类型掺杂的半导体沟道的封装的栅极结场效应晶体管（JFET）。所述至少一个半导体通道中的每一个的两个侧壁横向邻接具有第二导电类型掺杂的侧栅极区域，其与第一导电掺杂相反。此外，至少一个半导体沟道垂直邻接顶部栅极区域和至少一个具有第二导电类型掺杂的底部栅极区域。包括侧栅极区域的栅极电极，顶栅极区域和至少一个底栅极区域围绕至少一个半导体通道中的每一个环绕，以提供电流的严格控制，即，低截止电流，通过所述至少一个半导体通道。通过采用多个通道，JFET可以提供高导通电流。

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