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1. 发明授权

US07329582B1 Methods for fabricating a semiconductor device, which include selectively depositing an electrically conductive material 有权
标题翻译：制造半导体器件的方法，其包括选择性地沉积导电材料
公开(公告)号：US07329582B1
公开(公告)日：2008-02-12
申请号：US11154785
申请日：2005-06-15
申请人： James Pan , Jonathan Byron Smith , Ming-Ren Lin
发明人： James Pan , Jonathan Byron Smith , Ming-Ren Lin
IPC分类号： H01L21/335
CPC分类号： H01L29/41775 , H01L21/2652 , H01L21/28247 , H01L21/28568 , H01L21/288 , H01L23/485 , H01L29/41783 , H01L29/66575 , H01L2924/0002 , H01L2924/00
摘要： Methods are provided for fabricating a semiconductor device having an impurity doped region in a silicon substrate. The method comprises forming a metal silicide layer electrically contacting the impurity doped region and depositing a conductive layer overlying and electrically contacting the metal silicide layer. A dielectric layer is deposited overlying the conductive layer and an opening is etched through the dielectric layer to expose a portion of the conductive layer. A conductive material is selectively deposited to fill the opening and to electrically contact the impurity doped region.
摘要翻译：提供了制造在硅衬底中具有杂质掺杂区的半导体器件的方法。该方法包括形成与杂质掺杂区电接触的金属硅化物层，并沉积覆盖并电接触金属硅化物层的导电层。沉积覆盖导电层的电介质层，并且通过电介质层蚀刻开口以暴露导电层的一部分。选择性地沉积导电材料以填充开口并与杂质掺杂区域电接触。

2. 发明授权

US07078278B2 Dual-metal CMOS transistors with tunable gate electrode work function and method of making the same 有权
标题翻译：具有可调栅电极功能的双金属CMOS晶体管及其制作方法
公开(公告)号：US07078278B2
公开(公告)日：2006-07-18
申请号：US10833073
申请日：2004-04-28
申请人： James Pan , Ming-Ren Lin
发明人： James Pan , Ming-Ren Lin
IPC分类号： H01L28/80
CPC分类号： H01L21/823835 , H01L21/28097 , H01L21/823842
摘要： A dual-metal CMOS arrangement and method of making the same provides a substrate and a plurality of NMOS devices and PMOS devices formed on the substrate. Each of the plurality of NMOS devices and PMOS devices have gate electrodes. Each NMOS gate electrode includes a first silicide region on the substrate and a first metal region on the first silicide region. The first silicide region of the NMOS gate electrode consists of a first silicide having a work function that is close to the conduction band of silicon. Each of the PMOS gate electrodes includes a second silicide region on the substrate and a second metal region on the second silicide region. The second silicide region of the PMOS gate electrode consists of a second silicide having a work function that is close to the valence band of silicon.
摘要翻译：双金属CMOS布置及其制造方法提供了形成在衬底上的衬底和多个NMOS器件和PMOS器件。多个NMOS器件和PMOS器件中的每一个具有栅电极。每个NMOS栅极包括衬底上的第一硅化物区域和第一硅化物区域上的第一金属区域。 NMOS栅电极的第一硅化物区域由具有接近硅导带的功函数的第一硅化物组成。每个PMOS栅极电极包括衬底上的第二硅化物区域和第二硅化物区域上的第二金属区域。 PMOS栅电极的第二硅化物区域由具有接近硅的价带的功函数的第二硅化物组成。

3. 发明申请

US20050245016A1 Dual-metal CMOS transistors with tunable gate electrode work function and method of making the same 有权
标题翻译：具有可调栅电极功能的双金属CMOS晶体管及其制作方法
公开(公告)号：US20050245016A1
公开(公告)日：2005-11-03
申请号：US10833073
申请日：2004-04-28
申请人： James Pan , Ming-Ren Lin
发明人： James Pan , Ming-Ren Lin
IPC分类号： H01L21/28 , H01L21/8238
CPC分类号： H01L21/823835 , H01L21/28097 , H01L21/823842
摘要： A dual-metal CMOS arrangement and method of making the same provides a substrate and a plurality of NMOS devices and PMOS devices formed on the substrate. Each of the plurality of NMOS devices and PMOS devices have gate electrodes. Each NMOS gate electrode includes a first silicide region on the substrate and a first metal region on the first silicide region. The first silicide region of the NMOS gate electrode consists of a first silicide having a work function that is close to the conduction band of silicon. Each of the PMOS gate electrodes includes a second silicide region on the substrate and a second metal region on the second silicide region. The second silicide region of the PMOS gate electrode consists of a second silicide having a work function that is close to the valence band of silicon.
摘要翻译：双金属CMOS布置及其制造方法提供了形成在衬底上的衬底和多个NMOS器件和PMOS器件。多个NMOS器件和PMOS器件中的每一个具有栅电极。每个NMOS栅极包括衬底上的第一硅化物区域和第一硅化物区域上的第一金属区域。 NMOS栅电极的第一硅化物区域由具有接近硅导带的功函数的第一硅化物组成。每个PMOS栅极电极包括衬底上的第二硅化物区域和第二硅化物区域上的第二金属区域。 PMOS栅电极的第二硅化物区域由具有接近硅的价带的功函数的第二硅化物组成。

4. 发明授权

US07422961B2 Method of forming isolation regions for integrated circuits 有权
标题翻译：形成集成电路隔离区的方法
公开(公告)号：US07422961B2
公开(公告)日：2008-09-09
申请号：US10389456
申请日：2003-03-14
申请人： Haihong Wang , Minh-Van Ngo , Qi Xiang , Paul R. Besser , Eric N. Paton , Ming-Ren Lin
发明人： Haihong Wang , Minh-Van Ngo , Qi Xiang , Paul R. Besser , Eric N. Paton , Ming-Ren Lin
IPC分类号： H01L21/762
CPC分类号： H01L21/76224 , H01L21/823481 , H01L29/1054
摘要： A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be a CVD process.
摘要翻译：集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。浅沟槽隔离技术用于应变硅（SMOS）工艺。用于沟槽的衬垫由半导体或金属层形成，该半导体或金属层在低温过程中沉积，这降低了锗除气。低温工艺可以是CVD工艺。

5. 发明申请

US20080054316A1 STRAINED FULLY DEPLETED SILICON ON INSULATOR SEMICONDUCTOR DEVICE 有权
标题翻译：绝缘子半导体器件上残留的全部绝缘硅
公开(公告)号：US20080054316A1
公开(公告)日：2008-03-06
申请号：US11926655
申请日：2007-10-29
申请人： Qi Xiang , Niraj Subba , Witold Maszara , Zoran Krivokapic , Ming-Ren Lin
发明人： Qi Xiang , Niraj Subba , Witold Maszara , Zoran Krivokapic , Ming-Ren Lin
IPC分类号： H01L29/78
CPC分类号： H01L29/66772 , H01L29/66636 , H01L29/7842 , H01L29/7848 , H01L29/78639 , H01L29/78684 , Y10S438/938
摘要： A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor layer and the insulator are removed outside the spacer. Recessed source/drain are formed outside the spacer.
摘要翻译：提供了一种在绝缘体上具有半导体层的绝缘体的半导体衬底。形成深沟槽隔离，向半导体层引入应变。栅极电介质和栅极形成在半导体层上。在栅极周围形成间隔物，并且将半导体层和绝缘体去除在间隔物的外部。凹陷的源极/漏极形成在间隔物外部。

6. 发明申请

US20060177998A1 FULLY SILICIDED GATE STRUCTURE FOR FINFET DEVICES 有权
标题翻译： FINFET器件的完全硅胶结构
公开(公告)号：US20060177998A1
公开(公告)日：2006-08-10
申请号：US11379435
申请日：2006-04-20
申请人： Ming-Ren Lin , Witold Maszara , Haihong Wang , Bin Yu
发明人： Ming-Ren Lin , Witold Maszara , Haihong Wang , Bin Yu
IPC分类号： H01L21/3205
CPC分类号： H01L29/785 , H01L29/4908 , H01L29/66795 , H01L29/7842
摘要： A method may include forming a gate electrode over a fin structure, depositing a first metal layer on a top surface of the gate electrode, performing a first silicide process to convert a portion of the gate electrode into a metal-silicide compound, depositing a second metal layer on a top surface of the metal-silicide compound, and performing a second silicide process to form a fully-silicided gate electrode.
摘要翻译：一种方法可以包括在鳍结构上形成栅电极，在栅电极的顶表面上沉积第一金属层，执行第一硅化工艺以将栅电极的一部分转化为金属硅化物，在金属硅化物化合物的顶表面上的金属层，并且执行第二硅化物处理以形成全硅化物栅电极。

7. 发明授权

US06858503B1 Depletion to avoid cross contamination 失效
标题翻译：消耗以避免交叉污染
公开(公告)号：US06858503B1
公开(公告)日：2005-02-22
申请号：US10358484
申请日：2003-02-05
申请人： Minh V. Ngo , Ming-Ren Lin , Paul R. Besser , Qi Xiang , Eric N. Paton , Jung-Suk Goo
发明人： Minh V. Ngo , Ming-Ren Lin , Paul R. Besser , Qi Xiang , Eric N. Paton , Jung-Suk Goo
IPC分类号： H01L21/306 , H01L29/10 , H01L21/336
CPC分类号： H01L21/02046 , H01L29/1054
摘要： A fabrication system utilizes a protocol for removing germanium from a top surface of a wafer. An exposure to a gas, such as a gas containing the hydrochloric acid can remove germanium from the top surface. The protocol can allow shared equipment to be used in both Flash product fabrication lines and strained silicon (SMOS) fabrication lines. The protocol allows better silicidation in SMOS devices.
摘要翻译：制造系统利用从晶片顶表面去除锗的方案。暴露于气体，如含有盐酸的气体，可以从上表面除去锗。该协议可以允许在Flash产品制造线和应变硅（SMOS）生产线中使用共享设备。该协议允许在SMOS器件中更好的硅化。

8. 发明授权

US06764966B1 Spacers with a graded dielectric constant for semiconductor devices having a high-K dielectric 有权
标题翻译：具有高K电介质的半导体器件具有渐变介电常数的间隔物
公开(公告)号：US06764966B1
公开(公告)日：2004-07-20
申请号：US10085278
申请日：2002-02-27
申请人： William George En , Arvind Halliyal , Ming-Ren Lin , Minh Van Ngo , Chih-Yuh Yang
发明人： William George En , Arvind Halliyal , Ming-Ren Lin , Minh Van Ngo , Chih-Yuh Yang
IPC分类号： H01L2128
CPC分类号： H01L29/6656 , H01L29/66833 , H01L29/78
摘要： A semiconductor device formed on a semiconductor substrate having an active region and a method of making the same is disclosed. The semiconductor device includes a dielectric layer interposed between a gate electrode and the semiconductor substrate. Further, the semiconductor device includes graded dielectric constant spacers formed on sidewalls of the dielectric layer, sidewalls of the gate electrode and portions of an upper surface of the semiconductor substrate. The dielectric constant of the graded dielectric constant spacers decreases in a direction away from the sidewalls of the dielectric layer.
摘要翻译：公开了一种形成在具有有源区的半导体衬底上的半导体器件及其制造方法。半导体器件包括插入在栅电极和半导体衬底之间的电介质层。此外，半导体器件包括形成在电介质层的侧壁，栅电极的侧壁和半导体衬底的上表面的部分上的渐变介电常数间隔物。梯度介电常数间隔物的介电常数在远离介电层的侧壁的方向上减小。

9. 发明授权

US06670260B1 Transistor with local insulator structure 失效
标题翻译：具有局部绝缘体结构的晶体管
公开(公告)号：US06670260B1
公开(公告)日：2003-12-30
申请号：US09577332
申请日：2000-05-24
申请人： Bin Yu , Ming-Ren Lin , Shekhar Pramanick
发明人： Bin Yu , Ming-Ren Lin , Shekhar Pramanick
IPC分类号： H01L21425
CPC分类号： H01L29/6659 , H01L29/0649 , H01L29/78
摘要： A thin filmed fully-depleted silicon-on-insulator (SOI) metal oxide semiconductor field defect transistor (MOSFET) utilizes a local insulation structure. The local insulative structure includes a buried silicon dioxide region under the channel region. The MOSFET body thickness is very small and yet silicon available outside of the channel region and buried silicon dioxide region is available for sufficient depths of silicide in the source and drain regions. The buried silicon dioxide region can be formed by a trench isolation technique or a LOCOS technique.
摘要翻译：薄膜完全耗尽的绝缘体上硅（SOI）金属氧化物半导体场缺陷晶体管（MOSFET）利用局部绝缘结构。局部绝缘结构包括沟道区下方的埋置二氧化硅区域。 MOSFET体的厚度非常小，而在沟道区域和掩埋的二氧化硅区域之外可用的硅可用于源极和漏极区域中足够的硅化物深度。掩埋的二氧化硅区域可以通过沟槽隔离技术或LOCOS技术形成。

10. 发明授权

US06342438B2 Method of manufacturing a dual doped CMOS gate 有权
标题翻译：制造双掺杂CMOS栅极的方法
公开(公告)号：US06342438B2
公开(公告)日：2002-01-29
申请号：US09187379
申请日：1998-11-06
申请人： Bin Yu , Ming-Ren Lin
发明人： Bin Yu , Ming-Ren Lin
IPC分类号： H01L21265
CPC分类号： H01L21/823842 , H01L21/26506 , H01L21/26513 , H01L21/823871
摘要： A dual doped CMOS gate structure utilizes a nitrogen implant to suppress dopant inter-diffusion. The nitrogen implant is provided above standard trench isolation structures. Alternatively, an oxygen implant can be utilized. The use of the implant allows an increase in packing density for ultra-large-scale integrated (ULSI) circuits. The doping for N-channel and P-channel active regions can be completed when the polysilicon gate structures are doped.
摘要翻译：双掺杂CMOS栅极结构利用氮注入来抑制掺杂剂相互扩散。在标准沟槽隔离结构之上提供氮注入。或者，可以使用氧注入。使用植入物可以提高超大规模集成（ULSI）电路的封装密度。当掺杂多晶硅栅极结构时，可以完成N沟道和P沟道有源区的掺杂。

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