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    • 5. 发明授权
    • Process for planarization of metal-filled trenches of integrated circuit structures by forming a layer of planarizable material over the metal layer prior to planarizing
    • 在平坦化之前通过在金属层上形成可平面化材料层来平坦化集成电路结构的金属填充沟槽的方法
    • US06417093B1
    • 2002-07-09
    • US09703745
    • 2000-10-31
    • James J. XieRonald J. NagaharaJayanthi PallintiAkihisa Ueno
    • James J. XieRonald J. NagaharaJayanthi PallintiAkihisa Ueno
    • H01L214763
    • H01L21/3212H01L21/7684
    • A process for forming an integrated circuit structure wherein trenches and/or vias are formed in a predetermined pattern in a dielectric layer, lined with a barrier layer of a first electrically conductive material, and then filled with a second electrically conductive material, and the structure is then planarized to remove the first and second electrically conductive material from the upper surface of the dielectric layer, wherein the improvements comprise: a) before the planarizing step, forming over the second electrically conductive material a layer of a planarizable material capable of being planarized at about the same rate as the first electrically conductive material; and b) then planarizing the structure to remove: i) the planarizable material; ii) the second electrically conductive material; and iii) the first electrically conductive material; above the upper surface of the dielectric material; whereby the planarizable material above the second electrically conductive material in the trenches protects the second electrically conductive material while the first electrically conductive material is being removed from the upper surface of the dielectric layer by the planarizing step to prevent erosion of the upper surface of the second electrically conductive layer.
    • 一种用于形成集成电路结构的方法,其中沟槽和/或通孔以介电层形成为预定图案,衬有第一导电材料的阻挡层,然后填充有第二导电材料,并且结构 然后被平坦化以从电介质层的上表面去除第一和第二导电材料,其中改进包括:a)在平坦化步骤之前,在第二导电材料上形成能够被平坦化的可平面化材料层 以与第一导电材料大致相同的速率; 然后平面化结构以移除:i)可平面化材料; ii)第二导电材料; 和ii)第一导电材料;在电介质材料的上表面之上;由此沟槽中的第二导电材料上方的可平面化材料保护第二导电材料,同时第一导电材料从第二导电材料的上表面 所述介电层通过所述平坦化步骤来防止所述第二导电层的上表面的侵蚀。
    • 6. 发明授权
    • Semiconductor component and method of manufacture
    • 半导体元件及制造方法
    • US06927113B1
    • 2005-08-09
    • US10444353
    • 2003-05-23
    • Kashmir S. SahotaJeremy MartinRichard J. HuangJames J. Xie
    • Kashmir S. SahotaJeremy MartinRichard J. HuangJames J. Xie
    • H01L21/768H01L21/8238H01L23/532
    • H01L21/76811H01L21/76835H01L21/7684H01L21/76849H01L23/53238H01L23/5329H01L2924/0002H01L2924/00
    • A semiconductor component and a method for manufacturing the semiconductor component that mitigates electromigration and stress migration in a metallization system of the semiconductor component. A hardmask is formed over a dielectric layer and an opening is etched through the hardmask and into the dielectric layer. The opening is lined with a barrier layer and filled with an electrically conductive material. The electrically conductive material is planarized, where the planarization process stops on the barrier layer. Following planarization, the electrically conductive material is recessed using either an over-polishing process with highly selective copper slurry or a wet etching process to partially re-open the filled metal-filled trench or via. The recess process is performed such that the exposed portion of the electrically conductive material is below the dielectric layer. A capping layer is then deposited on both the dielectric portion and the exposed metal interconnect portion of the electrically conductive material.
    • 一种半导体部件和用于制造半导体部件的方法,其减轻半导体部件的金属化系统中的迁移和应力迁移。 在介电层上形成硬掩模,并且通过硬掩模蚀刻开口并进入电介质层。 开口衬有阻挡层并填充有导电材料。 导电材料被平坦化,其中平坦化处理在阻挡层上停止。 在平坦化之后,使用具有高选择性铜浆料的过度抛光工艺或湿式蚀刻工艺来使导电材料凹陷,以部分地重新打开填充的填充有金属的沟槽或通孔。 执行凹陷处理,使得导电材料的暴露部分在介电层之下。 然后在电介质部分和导电材料的暴露的金属互连部分上沉积覆盖层。
    • 10. 发明授权
    • Method for CMP endpoint detection
    • CMP端点检测方法
    • US06372524B1
    • 2002-04-16
    • US09946895
    • 2001-09-05
    • James J. XieJayanthi PallintiRonald J. Nagahara
    • James J. XieJayanthi PallintiRonald J. Nagahara
    • H01L2100
    • H01L22/26
    • A method for planarizing an integrated circuit on a substrate to a target surface of the substrate where at least portions of the target surface are of a first material having a first reflectivity. The substrate is overlaid with a top layer of a second material having a second reflectivity thereby forming an upper surface. Material is removed from the upper surface in a planarizing process, and the first reflectivity and second reflectivity of the upper surface are sensed with multiple wavelengths of electromagnetic radiation. The planarization process is stopped when a ratio of the second reflectivity to the first reflectivity equals a predetermined value.
    • 一种用于将基板上的集成电路平坦化到基板的目标表面的方法,其中目标表面的至少一部分是具有第一反射率的第一材料。 衬底覆盖有具有第二反射率的第二材料的顶层,从而形成上表面。 在平坦化处理中从上表面去除材料,并且利用多个电磁辐射波长来感测上表面的第一反射率和第二反射率。 当第二反射率与第一反射率的比等于预定值时,停止平坦化处理。