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1. 发明授权

US06417093B1 Process for planarization of metal-filled trenches of integrated circuit structures by forming a layer of planarizable material over the metal layer prior to planarizing 有权
标题翻译：在平坦化之前通过在金属层上形成可平面化材料层来平坦化集成电路结构的金属填充沟槽的方法
公开(公告)号：US06417093B1
公开(公告)日：2002-07-09
申请号：US09703745
申请日：2000-10-31
申请人： James J. Xie , Ronald J. Nagahara , Jayanthi Pallinti , Akihisa Ueno
发明人： James J. Xie , Ronald J. Nagahara , Jayanthi Pallinti , Akihisa Ueno
IPC分类号： H01L214763
CPC分类号： H01L21/3212 , H01L21/7684
摘要： A process for forming an integrated circuit structure wherein trenches and/or vias are formed in a predetermined pattern in a dielectric layer, lined with a barrier layer of a first electrically conductive material, and then filled with a second electrically conductive material, and the structure is then planarized to remove the first and second electrically conductive material from the upper surface of the dielectric layer, wherein the improvements comprise: a) before the planarizing step, forming over the second electrically conductive material a layer of a planarizable material capable of being planarized at about the same rate as the first electrically conductive material; and b) then planarizing the structure to remove: i) the planarizable material; ii) the second electrically conductive material; and iii) the first electrically conductive material; above the upper surface of the dielectric material; whereby the planarizable material above the second electrically conductive material in the trenches protects the second electrically conductive material while the first electrically conductive material is being removed from the upper surface of the dielectric layer by the planarizing step to prevent erosion of the upper surface of the second electrically conductive layer.
摘要翻译：一种用于形成集成电路结构的方法，其中沟槽和/或通孔以介电层形成为预定图案，衬有第一导电材料的阻挡层，然后填充有第二导电材料，并且结构然后被平坦化以从电介质层的上表面去除第一和第二导电材料，其中改进包括：a）在平坦化步骤之前，在第二导电材料上形成能够被平坦化的可平面化材料层以与第一导电材料大致相同的速率; 然后平面化结构以移除：i）可平面化材料; ii）第二导电材料; 和ii）第一导电材料;在电介质材料的上表面之上;由此沟槽中的第二导电材料上方的可平面化材料保护第二导电材料，同时第一导电材料从第二导电材料的上表面所述介电层通过所述平坦化步骤来防止所述第二导电层的上表面的侵蚀。

2. 发明授权

US06503828B1 Process for selective polishing of metal-filled trenches of integrated circuit structures 有权
标题翻译：用于选择性抛光集成电路结构的金属填充沟槽的工艺
公开(公告)号：US06503828B1
公开(公告)日：2003-01-07
申请号：US09882124
申请日：2001-06-14
申请人： Ronald J. Nagahara , James J. Xie , Akihisa Ueno , Jayanthi Pallinti
发明人： Ronald J. Nagahara , James J. Xie , Akihisa Ueno , Jayanthi Pallinti
IPC分类号： H01L214763
CPC分类号： H01L21/3212 , H01L21/7684
摘要： The invention provides a process for selectively polishing a main electrically conductive layer of an integrated circuit structure by the steps of forming a polishing barrier layer over depressed regions of the main electrically conductive layer; and polishing the portion of the main electrically conductive layer not covered by the polishing barrier layer. The integrated circuit structure treated by the process of the invention contains one or more openings in a layer of dielectric material, and the main electrically conductive layer fills the one or more openings such that the depressed regions of the main electrically conductive layer overlie said one or more openings.
摘要翻译：本发明提供了一种通过在主导电层的凹陷区域上形成抛光阻挡层的步骤来选择性地研磨集成电路结构的主导电层的工艺; 并且抛光未被抛光阻挡层覆盖的主导电层的部分。通过本发明的方法处理的集成电路结构在介电材料层中包含一个或多个开口，并且主导电层填充一个或多个开口，使得主导电层的凹陷区域覆盖所述一个或多个更多开口

3. 发明授权

US06340434B1 Method and apparatus for chemical-mechanical polishing 有权
标题翻译：化学机械抛光方法和装置
公开(公告)号：US06340434B1
公开(公告)日：2002-01-22
申请号：US09148028
申请日：1998-09-03
申请人： Hiroshi Mizuno , Osamu Kinoshita , Tetsuaki Murohashi , Akihisa Ueno , Yoshifumi Sakuma , Kostas Amberiadis
发明人： Hiroshi Mizuno , Osamu Kinoshita , Tetsuaki Murohashi , Akihisa Ueno , Yoshifumi Sakuma , Kostas Amberiadis
IPC分类号： H01L21302
CPC分类号： B24B37/013 , B24B37/042 , B24B49/006 , B24B49/16 , H01L21/3212
摘要： A method for chemical-mechanical polishing of a layer that is deposited on a surface of an integrated circuit substrate is described. The method includes: (1) immobilizing the integrated circuit substrate using a substrate holder such that the integrated circuit substrate surface is positioned against a surface of a polishing pad, which is mounted on a supporting surface; (2) a first stage of polishing the substrate surface including maintaining a predetermined difference between the rotational velocity of the polishing pad and the rotational velocity of the substrate holder allowing an endpoint of the chemical-mechanical polishing process of the layer to be detected; and (3) a second stage of polishing the substrate such that the rotational velocity of the polishing pad and the rotational velocity of the substrate holder are substantially the same to produce a substantially planar substrate surface.
摘要翻译：描述了沉积在集成电路基板的表面上的层的化学机械抛光的方法。该方法包括：（1）使用衬底保持器固定集成电路衬底，使得集成电路衬底表面抵靠安装在支撑表面上的抛光垫的表面; （2）抛光衬底表面的第一阶段，包括保持抛光垫的旋转速度和衬底保持器的旋转速度之间的预定差异，从而允许检测该层的化学 - 机械抛光工艺的终点; 和（3）抛光衬底的第二阶段，使得抛光垫的旋转速度和衬底保持器的旋转速度基本上相同以产生基本平坦的衬底表面。

4. 发明申请

US20080088271A1 Device of pulse width modulation type for load drive 有权
标题翻译：用于负载驱动的脉宽调制型装置
公开(公告)号：US20080088271A1
公开(公告)日：2008-04-17
申请号：US11907340
申请日：2007-10-11
申请人： Akihisa Ueno , Fumihisa Watanabe , Daijiro Arisawa
发明人： Akihisa Ueno , Fumihisa Watanabe , Daijiro Arisawa
IPC分类号： H02P23/00
CPC分类号： H02M7/5395 , H02M7/487
摘要： A device of pulse width modulation type for load drive according to the present invention includes a first output unit (3) that applies a first output signal (e) to a load (5) in response to a first drive timing signal (c), a second output unit (4) that applies a second output signal (f) to the load (5) in response to a second drive timing signal (d), a signal converter (1) that converts a drive input signal (a) into a parallel signal (b), the drive input signal indicating time information allowing a potential difference to be generated across the load (5), and a drive timing generator (2) that generates the first and second drive timing signals (c, d) in response to the parallel signal (b), the load (5) being driven by increasing and reducing pulse widths of the first and second output signals (e, f).
摘要翻译：根据本发明的用于负载驱动的脉宽调制型装置包括响应于第一驱动定时信号（c）将第一输出信号（e）施加到负载（5）的第一输出单元（3）响应于第二驱动定时信号（d）将负载（5）施加第二输出信号（f）的第二输出单元（4），将驱动输入信号（a）转换成并行信号（b），指示允许在所述负载（5）之间产生电位差的时间信息的所述驱动输入信号;以及产生所述第一和第二驱动定时信号（c，d）的驱动定时发生器（2）响应于并行信号（b），通过增加和减少第一和第二输出信号（e，f）的脉冲宽度来驱动负载（5）。

5. 发明授权

US07656113B2 Device of pulse width modulation type for load drive 有权
标题翻译：用于负载驱动的脉宽调制型装置
公开(公告)号：US07656113B2
公开(公告)日：2010-02-02
申请号：US11907340
申请日：2007-10-11
申请人： Akihisa Ueno , Fumihisa Watanabe , Daijiro Arisawa
发明人： Akihisa Ueno , Fumihisa Watanabe , Daijiro Arisawa
IPC分类号： H02P7/29 , G05B11/28 , H03K7/00
CPC分类号： H02M7/5395 , H02M7/487
摘要： A device of pulse width modulation type for load drive according to the present invention includes a first output unit (3) that applies a first output signal (e) to a load (5) in response to a first drive timing signal (c), a second output unit (4) that applies a second output signal (f) to the load (5) in response to a second drive timing signal (d), a signal converter (1) that converts a drive input signal (a) into a parallel signal (b), the drive input signal indicating time information allowing a potential difference to be generated across the load (5), and a drive timing generator (2) that generates the first and second drive timing signals (c, d) in response to the parallel signal (b), the load (5) being driven by increasing and reducing pulse widths of the first and second output signals (e, f).
摘要翻译：根据本发明的用于负载驱动的脉宽调制型装置包括响应于第一驱动定时信号（c）将第一输出信号（e）施加到负载（5）的第一输出单元（3）响应于第二驱动定时信号（d）将负载（5）施加第二输出信号（f）的第二输出单元（4），将驱动输入信号（a）转换成并行信号（b），指示允许在所述负载（5）之间产生电位差的时间信息的所述驱动输入信号;以及产生所述第一和第二驱动定时信号（c，d）的驱动定时发生器（2）响应于并行信号（b），通过增加和减少第一和第二输出信号（e，f）的脉冲宽度来驱动负载（5）。

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