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1. 发明授权

US07329905B2 Chip-scale methods for packaging light emitting devices and chip-scale packaged light emitting devices 有权
标题翻译：用于封装发光器件和芯片级封装发光器件的芯片级方法
公开(公告)号：US07329905B2
公开(公告)日：2008-02-12
申请号：US11171893
申请日：2005-06-30
申请人： James Ibbetson , Bernd Keller , Primit Parikh
发明人： James Ibbetson , Bernd Keller , Primit Parikh
IPC分类号： H01L29/22 , H01L29/227 , H01L33/00
CPC分类号： H01L33/486 , H01L23/481 , H01L24/48 , H01L33/62 , H01L2224/05001 , H01L2224/05023 , H01L2224/0508 , H01L2224/051 , H01L2224/05568 , H01L2224/056 , H01L2224/16 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/00014 , H01L2924/01004 , H01L2924/01078 , H01L2924/01079 , H01L2924/12035 , H01L2924/12041 , H01L2924/12042 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A packaged light emitting device includes a carrier substrate having a top surface and a bottom surface, first and second conductive vias extending from the top surface of the substrate to the bottom surface of the substrate, and a bond pad on the top surface of the substrate in electrical contact with the first conductive via. A diode having first and second electrodes is mounted on the bond pad with the first electrode is in electrical contact with the bond pad. A passivation layer is formed on the diode, exposing the second electrode of the diode. A conductive trace is formed on the top surface of the carrier substrate in electrical contact with the second conductive via and the second electrode. The conductive trace is on and extends across the passivation layer to contact the second electrode.Methods of packaging light emitting devices include providing an epiwafer including a growth substrate and an epitaxial structure on the growth substrate, bonding a carrier substrate to the epitaxial structure of the epiwafer, forming a plurality of conductive vias through the carrier substrate, defining a plurality of isolated diodes in the epitaxial structure, and electrically connecting at least one conductive via to respective ones of the plurality of isolated diodes.
摘要翻译：封装的发光器件包括具有顶表面和底表面的载体衬底，从衬底的顶表面延伸到衬底的底表面的第一和第二导电通孔以及衬底的顶表面上的接合焊盘与第一导电通孔电接触。具有第一和第二电极的二极管安装在接合焊盘上，第一电极与接合焊盘电接触。在二极管上形成钝化层，使二极管的第二电极露出。导电迹线形成在载体基板的顶表面上，与第二导电通孔和第二电极电接触。导电迹线在钝化层上并且延伸穿过第二电极。封装发光器件的方法包括在生长衬底上提供包括生长衬底和外延结构的外延膜，将载体衬底结合到外延膜的外延结构，形成通过载体衬底的多个导电通孔，限定多个隔离二极管，并且将至少一个导电通孔电连接到多个隔离二极管中的相应二极管。

2. 发明申请

US20080142817A1 CHIP-SCALE METHODS FOR PACKAGING LIGHT EMITTING DEVICES AND CHIP-SCALE PACKAGED LIGHT EMITTING DEVICES 有权
标题翻译：用于包装发光装置和芯片尺寸的包装光发射装置的芯片尺寸方法
公开(公告)号：US20080142817A1
公开(公告)日：2008-06-19
申请号：US12027313
申请日：2008-02-07
申请人： James Ibbetson , Bernd Keller , Primit Parikh
发明人： James Ibbetson , Bernd Keller , Primit Parikh
IPC分类号： H01L33/00 , H01L21/02
CPC分类号： H01L33/62 , H01L33/0079 , H01L33/483 , H01L33/486 , H01L33/60 , H01L2224/32245 , H01L2224/32257 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/00014 , H01L2924/00
摘要： A packaged light emitting device includes a carrier substrate having a top surface and a bottom surface, first and second conductive vias extending from the top surface of the substrate to the bottom surface of the substrate, and a bond pad on the top surface of the substrate in electrical contact with the first conductive via. A diode having first and second electrodes is mounted on the bond pad with the first electrode is in electrical contact with the bond pad. A passivation layer is formed on the diode, exposing the second electrode of the diode. A conductive trace is formed on the top surface of the carrier substrate in electrical contact with the second conductive via and the second electrode. The conductive trace is on and extends across the passivation layer to contact the second electrode.Methods of packaging light emitting devices include providing an epiwafer including a growth substrate and an epitaxial structure on the growth substrate, bonding a carrier substrate to the epitaxial structure of the epiwafer, forming a plurality of conductive vias through the carrier substrate, defining a plurality of isolated diodes in the epitaxial structure, and electrically connecting at least one conductive via to respective ones of the plurality of isolated diodes.
摘要翻译：封装的发光器件包括具有顶表面和底表面的载体衬底，从衬底的顶表面延伸到衬底的底表面的第一和第二导电通孔以及衬底的顶表面上的接合焊盘与第一导电通孔电接触。具有第一和第二电极的二极管安装在接合焊盘上，第一电极与接合焊盘电接触。在二极管上形成钝化层，使二极管的第二电极露出。导电迹线形成在载体基板的顶表面上，与第二导电通孔和第二电极电接触。导电迹线在钝化层上并且延伸穿过第二电极。封装发光器件的方法包括在生长衬底上提供包括生长衬底和外延结构的外延膜，将载体衬底结合到外延膜的外延结构，形成通过载体衬底的多个导电通孔，限定多个隔离二极管，并且将至少一个导电通孔电连接到多个隔离二极管中的相应二极管。

3. 发明授权

US07977686B2 Chip-scale methods for packaging light emitting devices and chip-scale packaged light emitting devices 有权
标题翻译：用于封装发光器件和芯片级封装发光器件的芯片级方法
公开(公告)号：US07977686B2
公开(公告)日：2011-07-12
申请号：US12027313
申请日：2008-02-07
申请人： James Ibbetson , Bernd Keller , Primit Parikh
发明人： James Ibbetson , Bernd Keller , Primit Parikh
IPC分类号： H01L29/18 , H01L33/00
CPC分类号： H01L33/62 , H01L33/0079 , H01L33/483 , H01L33/486 , H01L33/60 , H01L2224/32245 , H01L2224/32257 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/00014 , H01L2924/00
摘要： A packaged light emitting device includes a carrier substrate having a top surface and a bottom surface, first and second conductive vias extending from the top surface of the substrate to the bottom surface of the substrate, and a bond pad on the top surface of the substrate in electrical contact with the first conductive via. A diode having first and second electrodes is mounted on the bond pad with the first electrode is in electrical contact with the bond pad. A passivation layer is formed on the diode, exposing the second electrode of the diode. A conductive trace is formed on the top surface of the carrier substrate in electrical contact with the second conductive via and the second electrode. The conductive trace is on and extends across the passivation layer to contact the second electrode.
摘要翻译：封装的发光器件包括具有顶表面和底表面的载体衬底，从衬底的顶表面延伸到衬底的底表面的第一和第二导电通孔以及衬底的顶表面上的接合焊盘与第一导电通孔电接触。具有第一和第二电极的二极管安装在接合焊盘上，第一电极与接合焊盘电接触。在二极管上形成钝化层，使二极管的第二电极露出。导电迹线形成在载体基板的顶表面上，与第二导电通孔和第二电极电接触。导电迹线在钝化层上并且延伸穿过第二电极。

4. 发明申请

US20060006404A1 Chip-scale methods for packaging light emitting devices and chip-scale packaged light emitting devices 有权
标题翻译：用于封装发光器件和芯片级封装发光器件的芯片级方法
公开(公告)号：US20060006404A1
公开(公告)日：2006-01-12
申请号：US11171893
申请日：2005-06-30
申请人： James Ibbetson , Bernd Keller , Primit Parikh
发明人： James Ibbetson , Bernd Keller , Primit Parikh
IPC分类号： H01L29/22 , H01L21/00
CPC分类号： H01L33/486 , H01L23/481 , H01L24/48 , H01L33/62 , H01L2224/05001 , H01L2224/05023 , H01L2224/0508 , H01L2224/051 , H01L2224/05568 , H01L2224/056 , H01L2224/16 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/00014 , H01L2924/01004 , H01L2924/01078 , H01L2924/01079 , H01L2924/12035 , H01L2924/12041 , H01L2924/12042 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A packaged light emitting device includes a carrier substrate having a top surface and a bottom surface, first and second conductive vias extending from the top surface of the substrate to the bottom surface of the substrate, and a bond pad on the top surface of the substrate in electrical contact with the first conductive via. A diode having first and second electrodes is mounted on the bond pad with the first electrode is in electrical contact with the bond pad. A passivation layer is formed on the diode, exposing the second electrode of the diode. A conductive trace is formed on the top surface of the carrier substrate in electrical contact with the second conductive via and the second electrode. The conductive trace is on and extends across the passivation layer to contact the second electrode. Methods of packaging light emitting devices include providing an epiwafer including a growth substrate and an epitaxial structure on the growth substrate, bonding a carrier substrate to the epitaxial structure of the epiwafer, forming a plurality of conductive vias through the carrier substrate, defining a plurality of isolated diodes in the epitaxial structure, and electrically connecting at least one conductive via to respective ones of the plurality of isolated diodes.
摘要翻译：封装的发光器件包括具有顶表面和底表面的载体衬底，从衬底的顶表面延伸到衬底的底表面的第一和第二导电通孔以及衬底的顶表面上的接合焊盘与第一导电通孔电接触。具有第一和第二电极的二极管安装在接合焊盘上，第一电极与接合焊盘电接触。在二极管上形成钝化层，使二极管的第二电极露出。导电迹线形成在载体基板的顶表面上，与第二导电通孔和第二电极电接触。导电迹线在钝化层上并延伸穿过第二电极。封装发光器件的方法包括在生长衬底上提供包括生长衬底和外延结构的外延膜，将载体衬底结合到外延膜的外延结构，形成通过载体衬底的多个导电通孔，限定多个隔离二极管，并且将至少一个导电通孔电连接到多个隔离二极管中的相应二极管。

5. 发明授权

US09096939B2 Electrolysis transistor 有权
标题翻译：电解晶体管
公开(公告)号：US09096939B2
公开(公告)日：2015-08-04
申请号：US12156178
申请日：2008-05-29
申请人： Umesh Mishra , Rakesh Lai , Likun Shen , Lee McCarthy , Primit Parikh
发明人： Umesh Mishra , Rakesh Lai , Likun Shen , Lee McCarthy , Primit Parikh
IPC分类号： C25B9/00 , C25B9/04 , C02F1/461 , C25B1/02 , C25B11/00 , C25B15/00 , C25B11/04 , C25B1/00 , C25B1/04 , C25B1/06
CPC分类号： C25B1/02 , C25B1/003 , C25B1/04 , C25B1/06 , C25B9/04 , C25B11/00 , C25B11/0447 , C25B15/00 , Y02E60/366 , Y02P20/135
摘要： An electrolysis transistor for providing high-density electrochemistry and products utilizing the same, and high-efficiency electrolysis and electrochemical processes is disclosed. The electrolysis transistor may comprise an electrolyte, one or more working electrodes for transferring charge to or from said electrolyte, and one or more gate structures for altering electrode over-voltage and modifying the barrier at the electrode-electrolyte interface, reducing the voltage necessary for electrolysis. An electrochemical or photo-electrochemical cell may incorporate one or more of these electrolysis transistors.
摘要翻译：公开了一种用于提供高密度电化学的电解晶体管和利用其的产品，以及高效电解和电化学方法。电解晶体管可以包括电解质，用于将电荷转移到所述电解质或从所述电解质转移电荷的一个或多个工作电极，以及用于改变电极过电压并改变电极 - 电解质界面处的阻挡层的一个或多个栅极结构，电解。电化学或光电化学电池可并入这些电解晶体管中的一种或多种。

6. 发明授权

US09035354B2 Heterojunction transistors having barrier layer bandgaps greater than channel layer bandgaps and related methods 有权
标题翻译：具有比沟道层带隙更大的阻挡层带隙的异质结晶体管和相关方法
公开(公告)号：US09035354B2
公开(公告)日：2015-05-19
申请号：US12566973
申请日：2009-09-25
申请人： Adam William Saxler , Yifeng Wu , Primit Parikh
发明人： Adam William Saxler , Yifeng Wu , Primit Parikh
IPC分类号： H01L29/778 , H01L29/20 , H01L29/66 , H01L29/207 , H01L29/80
CPC分类号： H01L29/7785 , H01L29/2003 , H01L29/207 , H01L29/66462 , H01L29/7783 , H01L29/802
摘要： A heterojunction transistor may include a channel layer comprising a Group III nitride, a barrier layer comprising a Group III nitride on the channel layer, and an energy barrier comprising a layer of a Group III nitride including indium on the channel layer such that the channel layer is between the barrier layer and the energy barrier. The barrier layer may have a bandgap greater than a bandgap of the channel layer, and a concentration of indium (In) in the energy barrier may be greater than a concentration of indium (In) in the channel layer. Related methods are also discussed.
摘要翻译：异质结晶体管可以包括包含III族氮化物的沟道层，在沟道层上包含III族氮化物的势垒层，以及包括在沟道层上包含铟的III族氮化物层的能量势垒，使得沟道层在阻挡层和能量屏障之间。阻挡层可以具有大于沟道层的带隙的带隙，并且能量势垒中的铟（In）的浓度可以大于沟道层中的铟（In）的浓度。还讨论了相关方法。

7. 发明授权

US08669589B2 Robust transistors with fluorine treatment 有权
标题翻译：具有氟处理的坚固晶体管
公开(公告)号：US08669589B2
公开(公告)日：2014-03-11
申请号：US13112285
申请日：2011-05-20
申请人： Yifeng Wu , Marcia Moore , Tim Wisleder , Primit Parikh
发明人： Yifeng Wu , Marcia Moore , Tim Wisleder , Primit Parikh
IPC分类号： H01L29/66
CPC分类号： H01L29/7783 , H01L29/2003 , H01L29/207 , H01L29/402 , H01L29/66462
摘要： A semiconductor device, and particularly a high electron mobility transistor (HEMT), having a plurality of epitaxial layers and experiencing an operating (E) field. A negative ion region in the epitaxial layers to counter the operating (E) field. One method for fabricating a semiconductor device comprises providing a substrate and growing epitaxial layers on the substrate. Negative ions are introduced into the epitaxial layers to form a negative ion region to counter operating electric (E) fields in the semiconductor device. Contacts can be deposited on the epitaxial layers, either before or after formation of the negative ion region.
摘要翻译：具有多个外延层并经历操作（E）场的半导体器件，特别是高电子迁移率晶体管（HEMT）。在外延层中的负离子区域以对抗操作（E）场。制造半导体器件的一种方法包括在衬底上提供衬底和生长外延层。将负离子引入外延层中以形成负离子区域以对抗半导体器件中的电（E）场。可以在形成负离子区之前或之后将触点沉积在外延层上。

8. 发明申请

US20110193619A1 SEMICONDUCTOR ELECTRONIC COMPONENTS AND CIRCUITS 有权
标题翻译：半导体电子元件和电路
公开(公告)号：US20110193619A1
公开(公告)日：2011-08-11
申请号：US12701458
申请日：2010-02-05
申请人： Primit Parikh , James Honea , Carl C. Blake, JR. , Robert Coffie , Yifeng Wu , Umesh Mishra
发明人： Primit Parikh , James Honea , Carl C. Blake, JR. , Robert Coffie , Yifeng Wu , Umesh Mishra
IPC分类号： H03K3/01 , H01L27/06
CPC分类号： H01L27/0883 , H01L21/8258 , H01L23/49562 , H01L23/49575 , H01L23/642 , H01L23/647 , H01L25/165 , H01L25/18 , H01L27/0605 , H01L2224/48137 , H01L2224/48195 , H01L2224/48247 , H01L2224/48257 , H01L2924/1305 , H01L2924/13055 , H01L2924/13062 , H01L2924/13091 , H01L2924/30107 , H03K17/567 , H01L2924/00
摘要： An electronic component includes a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor both encased in a single package. A source electrode of the high-voltage depletion-mode transistor is electrically connected to a drain electrode of the low-voltage enhancement-mode transistor, a drain electrode of the high-voltage depletion-mode transistor is electrically connected to a drain lead of the single package, a gate electrode of the low-voltage enhancement-mode transistor is electrically connected to a gate lead of the single package, a gate electrode of the high-voltage depletion-mode transistor is electrically connected to an additional lead of the single package, and a source electrode of the low-voltage enhancement-mode transistor is electrically connected to a conductive structural portion of the single package.
摘要翻译：电子部件包括高压耗尽型晶体管和低压增强型晶体管，两者都封装在单个封装中。高电压耗尽型晶体管的源电极电连接到低电压增强型晶体管的漏电极，高电压耗尽型晶体管的漏极电连接到漏极引线单个封装，低电压增强型晶体管的栅电极电连接到单个封装的栅极引线，高电压耗尽型晶体管的栅极电连接到单个封装的附加引线并且低电压增强型晶体管的源电极电连接到单个封装的导电结构部分。

9. 发明申请

US20110127541A1 SEMICONDUCTOR HETEROSTRUCTURE DIODES 有权
标题翻译：半导体结构二极管
公开(公告)号：US20110127541A1
公开(公告)日：2011-06-02
申请号：US13008874
申请日：2011-01-18
申请人： Yifeng Wu , Umesh Mishra , Primit Parikh , Rongming Chu , Ilan Ben-Yaacov , Likun Shen
发明人： Yifeng Wu , Umesh Mishra , Primit Parikh , Rongming Chu , Ilan Ben-Yaacov , Likun Shen
IPC分类号： H01L29/02
CPC分类号： H01L29/0615 , H01L27/0629 , H01L29/2003 , H01L29/205 , H01L29/4236 , H01L29/778 , H01L29/7786 , H01L29/7787 , H01L29/872
摘要： Planar Schottky diodes for which the semiconductor material includes a heterojunction which induces a 2DEG in at least one of the semiconductor layers. A metal anode contact is on top of the upper semiconductor layer and forms a Schottky contact with that layer. A metal cathode contact is connected to the 2DEG, forming an ohmic contact with the layer containing the 2DEG.
摘要翻译：平面肖特基二极管，其半导体材料包括在至少一个半导体层中诱导2DEG的异质结。金属阳极触点位于上半导体层的顶部，与该层形成肖特基接触。金属阴极接触件连接到2DEG，与包含2DEG的层形成欧姆接触。

10. 发明申请

US20110114997A1 HIGH VOLTAGE GaN TRANSISTORS 有权
标题翻译：高电压GaN晶体管
公开(公告)号：US20110114997A1
公开(公告)日：2011-05-19
申请号：US13014619
申请日：2011-01-26
申请人： YIFENG WU , Primit Parikh , Umesh Mishra
发明人： YIFENG WU , Primit Parikh , Umesh Mishra
IPC分类号： H01L29/778
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/404 , H01L29/66462 , H01L29/7786
摘要： A multiple field plate transistor includes an active region, with a source, a drain, and a gate. A first spacer layer is over the active region between the source and the gate and a second spacer layer over the active region between the drain and the gate. A first field plate on the first spacer layer is connected to the gate. A second field plate on the second spacer layer is connected to the gate. A third spacer layer is on the first spacer layer, the second spacer layer, the first field plate, the gate, and the second field plate, with a third field plate on the third spacer layer and connected to the source. The transistor exhibits a blocking voltage of at least 600 Volts while supporting a current of at least 2 Amps with an on resistance of no more than 5.0 mΩ-cm2, of at least 600 Volts while supporting a current of at least 3 Amps with an on resistance of no more than 5.3 mΩ-cm2, of at least 900 Volts while supporting a current of at least 2 Amps with an on resistance of no more than 6.6 mΩ-cm2, or a blocking voltage of at least 900 Volts while supporting a current of at least 3 Amps with an on resistance of no more than 7.0 mΩ-cm2.
摘要翻译：多场板晶体管包括有源区，源极，漏极和栅极。第一间隔层在源极和栅极之间的有源区上方，并且在漏极和栅极之间的有源区上方具有第二间隔层。第一间隔层上的第一场板连接到栅极。第二间隔层上的第二场板连接到栅极。第三间隔层位于第一间隔层，第二间隔层，第一场板，栅极和第二场板上，在第三间隔层上具有第三场板并连接到源极。晶体管表现出至少600伏特的阻断电压，同时支持至少2安培的电流，其导通电阻不超过5.0mΩ（OHgr·-cm2）为至少600伏，同时支持至少3安培的电流耐电压不超过5.3mΩ，OHgr--cm2，至少900V，同时支持至少2安培的电流，导通电阻不超过6.6mΩ，OHgr-cm2，或阻断电压至少为900V，同时支持至少3安培的电流，导通电阻不超过7.0mΩ，OHgr; -cm2。

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