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1. 发明授权

US4933895A Cellular array having data dependent processing capabilities 失效
标题翻译：具有数据相关处理能力的蜂窝阵列
公开(公告)号：US4933895A
公开(公告)日：1990-06-12
申请号：US72195
申请日：1987-07-10
申请人： Jan Grinberg , James G. Nash , Michael J. Little
发明人： Jan Grinberg , James G. Nash , Michael J. Little
IPC分类号： G06F15/16 , G06F15/76 , G06F15/80
CPC分类号： G06F15/8023 , G06F15/8007
摘要： A cellular array processor (10) for efficiently performing data dependent processing such as floating point arithmetic functions. One module (84) in the array processor (12) generates a signal applied to bus line (24) when all of the bits in a register (86) are zero. The signal on bus line (24) effects the shifting operation of a shift register (36) in a memory module (34) located on a different functional plane. Thus, the processing functions carried out in each elemental processor (26) can be made to depend on the value of data stored therein instead of being dictated solely by a simultaneous executed instruction from the control processor (14) as is the normal case.
摘要翻译：一种用于有效执行诸如浮点运算功能的数据相关处理的蜂窝阵列处理器（10）。阵列处理器（12）中的一个模块（84）当寄存器（86）中的所有位都为零时，产生施加到总线（24）的信号。总线（24）上的信号实现位于不同功能平面上的存储器模块（34）中的移位寄存器（36）的移位操作。因此，如通常情况那样，可以使在每个元素处理器（26）中执行的处理功能取决于存储在其中的数据的值，而不是仅由来自控制处理器（14）的同时执行的指令来规定。

2. 发明授权

US07120658B2 Digital systolic array architecture and method for computing the discrete Fourier transform 有权
标题翻译：数字收缩阵列结构和计算离散傅里叶变换的方法
公开(公告)号：US07120658B2
公开(公告)日：2006-10-10
申请号：US10223176
申请日：2002-08-19
申请人： James G. Nash
发明人： James G. Nash
IPC分类号： G06F17/14
CPC分类号： G06F17/142 , G06F17/141
摘要： A more computationally efficient and scalable systolic architecture is provided for computing the discrete Fourier transform. The systolic architecture also provides a method for reducing the array area by limiting the number of complex multipliers. In one embodiment, the design improvement is achieved by taking advantage of a more efficient computation scheme based on symmetries in the Fourier transform coefficient matrix and the radix-4 butterfly. The resulting design provides an array comprised of a plurality of smaller base-4 matrices that can simply be added or removed to provide scalability of the design for applications involving different transform lengths to be calculated. In this embodiment, the systolic array size provides greater flexibility because it can be applied for use with any transform length which is an integer multiple of sixteen.
摘要翻译：提供了一种计算效率高且可扩展的收缩架构，用于计算离散傅里叶变换。收缩结构还提供了一种通过限制复数乘数来减少阵列面积的方法。在一个实施例中，通过利用基于傅立叶变换系数矩阵和基数-4蝴蝶中的对称性的更有效的计算方案来实现设计改进。所得到的设计提供了由多个较小的基础4矩阵组成的阵列，其可以简单地被添加或移除，以提供涉及要计算的不同变换长度的应用的设计的可扩展性。在该实施例中，收缩阵列尺寸提供了更大的灵活性，因为它可以应用于任何变形长度，其为十六进制的整数倍。

3. 发明授权

US4901360A Gated architecture for computer vision machine 失效
标题翻译：计算机视觉机器门控架构
公开(公告)号：US4901360A
公开(公告)日：1990-02-13
申请号：US113084
申请日：1987-10-23
申请人： David B. Shu , James G. Nash
发明人： David B. Shu , James G. Nash
IPC分类号： G06F15/80 , G06T1/20 , G06T7/00
CPC分类号： G06T1/20
摘要： A computer architecture 10 for performing iconic and symbolic operations on image data is disclosed. Three levels of processing elements (CAAPP, ICP, GPPA) are disclosed. The processing elements in the lowest level (CAAPP) are provided with a plurality of controllable gates (N, S, E, W, H, V, NW, NE) that are used to selectively connect together processing elements in that level. In such manner, certain algorithms such as the minimum spanning tree algorithm can be efficiently performed.
摘要翻译：公开了一种用于对图像数据执行图标和符号操作的计算机体系结构10。公开了三级处理要素（CAAPP，ICP，GPPA）。最低级（CAAPP）中的处理元件设置有多个可控制门（N，S，E，W，H，V，NW，NE），用于选择性地将处于该级别的处理元件连接在一起。以这种方式，可以有效地执行诸如最小生成树算法的某些算法。

4. 发明授权

US4809347A Computer vision architecture 失效
标题翻译：计算机视觉架构
公开(公告)号：US4809347A
公开(公告)日：1989-02-28
申请号：US887847
申请日：1986-07-18
申请人： James G. Nash , David B. Shu
发明人： James G. Nash , David B. Shu
IPC分类号： G06T7/00 , G06F15/80 , G06T1/20 , G06K9/00
CPC分类号： G06F15/8023 , G06T1/20
摘要： A computer architecture is disclosed for analyzing automatic image understanding problems. The architecture is designed so that it can efficiently perform a wide spectrum of tasks ranging from low level or iconic processing to high level or symbolic processing tasks. A first level (12) of image processing elements is provided for operating on the image matrix on a pixel per processing element basis. A second level (14) of processing elements is provided for operating on a plurality of pixels associated with a given array of first level processing elements. A third level (16) of processing elements is designed to instruct the first and second level processing elements, as well as for operating on a larger segment of the matrix. A host computer (18) is provided that directly communicates with at least each third level processing element. A high degree of parallelism is provided so that information can be readily transferred within the architecture at high speeds.
摘要翻译：公开了一种用于分析自动图像理解问题的计算机体系结构。该架构的设计使其能够有效地执行从低级别或标志性处理到高级别或符号处理任务的广泛任务。提供图像处理元件的第一级（12），用于基于每个处理元件的像素对图像矩阵进行操作。处理元件的第二级（14）被提供用于在与给定的第一级处理元件阵列相关联的多个像素上操作。处理元件的第三级（16）被设计为指示第一级和第二级处理元件以及用于在矩阵的较大段上操作。提供主机（18），其与至少每个第三级处理元件直接通信。提供高度的并行性，使得可以在架构内以高速度容易地传递信息。

5. 发明授权

US4811270A Merged CCD/MOS integrated circuit 失效
标题翻译：合并的CCD / MOS集成电路
公开(公告)号：US4811270A
公开(公告)日：1989-03-07
申请号：US788305
申请日：1985-10-17
申请人： James G. Nash
发明人： James G. Nash
IPC分类号： G06F7/52 , G06F7/00 , G06F7/16
CPC分类号： G06F7/533 , G06F7/5336 , G06F2207/4808
摘要： A digital integrated circuit that includes on a common substrate both charge-coupled device (CCD) circuitry and metal-oxide semiconductor (MOS) circuitry that combine together efficiently to implement a complex digital function such as a multi-bit multiplier or divider. The CCD circuitry includes an array of full adder cells and the MOS circuitry selectively processes and channels certain bits of a plurality of digital input bits to the individual full adder cells, such processing being based on other of the digital input bits. The introduction of MOS logic into the CCD circuit permits greater flexibility in the layout and interconnection of the individual full adder cells and permits the utilization of more efficient algorithms than otherwise could be used in circuits having CCD elements alone.
摘要翻译：一种数字集成电路，其包括在共同的基板上，电荷耦合器件（CCD）电路和金属氧化物半导体（MOS）电路组合在一起以有效地实现诸如多位乘法器或分频器之类的复数数字功能。 CCD电路包括全加器单元的阵列，并且MOS电路选择性地处理和通道多个数字输入位的某些位给各个全加器单元，这种处理基于其他数字输入位。将MOS逻辑引入CCD电路允许各个全加器单元的布局和互连中的更大的灵活性，并且允许使用比用于单独具有CCD元件的电路中更有效的算法。

6. 发明授权

US4464728A Charge coupled device ripple adder with nearly instantaneous carry propagation 失效
标题翻译：电荷耦合器件纹波加法器具有几乎瞬时的进位传播
公开(公告)号：US4464728A
公开(公告)日：1984-08-07
申请号：US303332
申请日：1981-09-18
申请人： James G. Nash
发明人： James G. Nash
IPC分类号： G06F7/505 , G06F7/50 , G06F7/501 , G06F7/506
CPC分类号： G06F7/501 , G06F2207/4808
摘要： A ripple adder is implemented as a charge coupled device in such a manner that each carry bit propagates between succeeding full adder stages substantially simultaneously as each stage computes the sum of its two bits, so that the addition in each full adder stage may be carried out in parallel rather than in succession. The i.sup.th one of the CCD full adder stages includes charge transfer means for receiving two bits of charge, namely the i.sup.th bits of the two n-bit words which are to be summed. First and second charge storage means are provided, each having the capacity to store one bit of charge only, so that excess charge will cause an overflow. Means for sensing overflow charge stored in the second charge storage means is connected to a carry bit charge injector in the i.sup.th +1 adder stage.
摘要翻译：波纹加法器被实现为电荷耦合器件，使得每个进位位基本上同时在后续的全加器级之间传播，因为每一级计算其两位的和，从而可以执行每个全加器级的相加并行而不是连续地。第一个CCD全加器级之一包括用于接收两位电荷的电荷转移装置，即要相加的两个n位字的第i位。提供第一和第二电荷存储装置，每个具有仅存储一位电荷的能力，使得过量的电荷将引起溢出。用于感测存储在第二电荷存储装置中的溢出电荷的装置在第i + 1个加法器级连接到进位位电荷注入器。

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