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1. 发明授权

US07118274B2 Method and reference circuit for bias current switching for implementing an integrated temperature sensor 失效
标题翻译：用于实现集成温度传感器的偏置电流开关的方法和参考电路
公开(公告)号：US07118274B2
公开(公告)日：2006-10-10
申请号：US10849580
申请日：2004-05-20
申请人： Nghia Van Phan , Patrick Lee Rosno , James David Strom
发明人： Nghia Van Phan , Patrick Lee Rosno , James David Strom
IPC分类号： G01K7/01 , G01K7/14 , G05F3/24 , G05F3/26
CPC分类号： G01K7/01
摘要： A method and a reference circuit for bias current switching are provided for implementing an integrated temperature sensor. A first bias current is generated and constantly applied to a thermal sensing diode. A second bias current is provided to the thermal sensing diode by selectively switching a multiplied current from a current multiplier to the thermal sensing diode or to a load diode. The reference circuit includes a reference current source coupled to current mirror. The current mirror provides a first bias current to a thermal sensing diode. The current mirror is coupled to a current multiplier that provides a multiplied current. A second bias current to the thermal sensing diode includes the first bias current and the multiplied current from the current multiplier. The second bias current to the thermal sensing diode is provided by selectively switching the multiplied current between the thermal sensing diode and a dummy load diode.
摘要翻译：提供了用于实现集成温度传感器的偏置电流切换的方法和参考电路。产生第一偏置电流并且恒定地施加到热感测二极管。通过选择性地将乘法电流从电流乘法器切换到热感测二极管或负载二极管，来向热感测二极管提供第二偏置电流。参考电路包括耦合到电流镜的参考电流源。电流镜向热敏二极管提供第一偏置电流。电流镜耦合到提供倍增电流的电流倍增器。到热敏二极管的第二偏置电流包括第一偏置电流和来自当前乘法器的相乘电流。通过选择性地切换热感测二极管和虚拟负载二极管之间的倍增电流来提供到热敏二极管的第二偏置电流。

2. 发明授权

US06724256B1 Receiver with delay insensitive to input amplitude and slew rate 失效
标题翻译：接收器对输入幅度和转换速率不敏感
公开(公告)号：US06724256B1
公开(公告)日：2004-04-20
申请号：US10289604
申请日：2002-11-07
申请人： James David Strom , Patrick Lee Rosno
发明人： James David Strom , Patrick Lee Rosno
IPC分类号： H03F345
CPC分类号： H03F3/45278 , H03F3/45085 , H03F2203/45646 , H03F2203/45652 , H03F2203/45722
摘要： A receiver is provided with delay generally insensitive to input amplitude and slew rate. The receiver includes a first differential transistor pair having a common emitter connection. A differential input is applied to a respective base of the differential transistor pair. A pair of load transistors is connected to the respective collector of the differential transistor pair. A respective resistance is coupled to a base of the load transistors for providing a delay independent of the differential input; and a pair of bias transistors is coupled to the respective collector of the differential transistor pair for biasing the load transistors.
摘要翻译：接收机具有对输入幅度和转换速率通常不敏感的延迟。接收器包括具有共同发射极连接的第一差分晶体管对。差分输入被施加到差分晶体管对的相应基极。一对负载晶体管连接到差分晶体管对的各个集电极。相应的电阻耦合到负载晶体管的基极，用于提供独立于差分输入的延迟; 并且一对偏置晶体管耦合到差分晶体管对的相应集电极以偏置负载晶体管。

3. 发明授权

US07173482B2 CMOS regulator for low headroom applications 失效
标题翻译： CMOS调节器用于低裕量应用
公开(公告)号：US07173482B2
公开(公告)日：2007-02-06
申请号：US11094711
申请日：2005-03-30
申请人： Katherine Ellen Lobb , Patrick Lee Rosno , James David Strom
发明人： Katherine Ellen Lobb , Patrick Lee Rosno , James David Strom
IPC分类号： G05F1/10
CPC分类号： G05F3/242
摘要： A complementary metal oxide semiconductor (CMOS) voltage regulator for low headroom applications includes a differential input common mode range amplifier. The differential input common mode range amplifier is formed by a plurality of CMOS transistors. A source follower CMOS transistor is coupled to an output of the differential input common mode range amplifier for providing an output of the CMOS voltage regulator. A current source is coupled to the differential input common mode range amplifier for maintaining a bias current through the differential input common mode range amplifier.
摘要翻译：用于低余量应用的互补金属氧化物半导体（CMOS）电压调节器包括差分输入共模范围放大器。差分输入共模范围放大器由多个CMOS晶体管形成。源极跟随器CMOS晶体管耦合到差分输入共模范围放大器的输出，用于提供CMOS电压调节器的输出。电流源耦合到差分输入共模范围放大器，用于保持偏置电流通过差分输入共模范围放大器。

4. 发明授权

US06670655B2 SOI CMOS device with body to gate connection 有权
公开(公告)号：US06670655B2
公开(公告)日：2003-12-30
申请号：US09837839
申请日：2001-04-18
申请人： Eric John Lukes , Patrick Lee Rosno , James David Strom
发明人： Eric John Lukes , Patrick Lee Rosno , James David Strom
IPC分类号： H01L27148
CPC分类号： H01L27/1203 , H01L29/783
摘要： A method and apparatus are provided for implementing a body contact in a silicon-on-insulator field effect transistor device. A SOI field effect transistor is provided having a body contact having a predefined resistance that provides a higher device threshold voltage in the SOI FET device. A body of the SOI field effect transistor is connected to the gate of the SOI field effect transistor. The body gate connection of the SOI field effect transistor effectively lowers the device threshold voltage due to body bias effect. The SOI field effect transistor with a body connected to the gate of the SOI field effect transistor is used in circuits having stacked devices and DC currents. The SOI field effect transistor with a body connected to the gate of the SOI field effect transistor also is used in analog circuits with device matching requirements and in circuits having a low voltage power supply.

5. 发明授权

US06859092B2 Method and low voltage CMOS circuit for generating voltage and current references 失效
标题翻译：用于产生电压和电流参考的方法和低压CMOS电路
公开(公告)号：US06859092B2
公开(公告)日：2005-02-22
申请号：US10418569
申请日：2003-04-17
申请人： Eric John Lukes , Patrick Lee Rosno , James David Strom , Dana Marie Woeste
发明人： Eric John Lukes , Patrick Lee Rosno , James David Strom , Dana Marie Woeste
IPC分类号： G05F1/46 , G05F1/10 , G05F3/02
CPC分类号： G05F1/46
摘要： A method and a low voltage, complementary metal oxide semiconductor (CMOS) circuit are provided for generating voltage and current references with a low voltage power supply. A voltage generating circuit provides a voltage reference and is formed by a plurality of CMOS transistors and a resistor. An operational amplifier includes a differential pair of CMOS transistors. The first voltage reference is applied to an input of the differential pair of transistors and an output of the differential pair of transistors providing a second voltage reference. The operational amplifier includes a plurality of current reference transistors. A first voltage generating circuit generates a first voltage and a second voltage generating circuit generating a second voltage. The first and second voltage generating circuits are formed by a plurality of CMOS transistors. The generated first and second voltages are applied to the voltage reference generating circuit and current reference transistors.
摘要翻译：提供一种方法和低电压互补金属氧化物半导体（CMOS）电路，用于利用低电压电源产生电压和电流参考。电压产生电路提供电压参考，并由多个CMOS晶体管和电阻器形成。运算放大器包括一对差分CMOS晶体管。第一参考电压被施加到晶体管的差分对的输入和提供第二电压基准的晶体管的差分对的输出。运算放大器包括多个电流参考晶体管。第一电压产生电路产生产生第二电压的第一电压和第二电压产生电路。第一和第二电压产生电路由多个CMOS晶体管形成。产生的第一和第二电压被施加到电压参考产生电路和电流参考晶体管。

6. 发明授权

US06693465B1 Open input sense for differential receiver 失效
标题翻译：差分接收器的开路输入检测
公开(公告)号：US06693465B1
公开(公告)日：2004-02-17
申请号：US10345558
申请日：2003-01-16
申请人： Patrick Lee Rosno , James David Strom
发明人： Patrick Lee Rosno , James David Strom
IPC分类号： H03K522
CPC分类号： H03K5/2481 , H04L25/08
摘要： Circuitry is disclosed for detection of open inputs on an enhanced differential receiver. A pulldown terminator is coupled to the inputs of the enhanced differential receiver. If the differential inputs are not actively driven, the voltage on both differential inputs will be pulled to a predetermined voltage. When the voltage on the differential inputs reach a reference voltage, an active device detects that the reference voltage has been reached, and produces a predetermined logic value on an output of the enhanced differential receiver. The enhanced differential receiver is not subject to oscillation when not actively driven. Delay through the enhanced differential receiver is not substantially greater than delay through a conventional differential receiver consisting of only a differential amplifier.
摘要翻译：公开了用于检测增强型差分接收器上的开放输入的电路。下拉终端器耦合到增强型差分接收器的输入端。如果差分输入未被主动驱动，则两个差分输入端的电压将被拉至预定的电压。当差分输入上的电压达到参考电压时，有源器件检测到已经达到参考电压，并且在增强差分接收器的输出上产生预定的逻辑值。增强型差分接收器不主动驱动时不会发生振荡。通过增强型差分接收器的延迟通过仅由差分放大器组成的常规差分接收器的延迟实质上不大。

7. 发明授权

US06535986B1 Optimizing performance of a clocked system by adjusting clock control settings and clock frequency 失效
标题翻译：通过调整时钟控制设置和时钟频率来优化时钟系统的性能
公开(公告)号：US06535986B1
公开(公告)日：2003-03-18
申请号：US09524878
申请日：2000-03-14
申请人： Patrick Lee Rosno , James David Strom
发明人： Patrick Lee Rosno , James David Strom
IPC分类号： G06F108
CPC分类号： G06F1/324 , G06F1/3203 , Y02D10/126
摘要： A method of adjusting the operating or timing margin of a clocked system, such as a digital computer or a memory controller, is disclosed. The method may be automated to occur upon every initial program load or can be manually adjusted for changes in frequency, operating voltages, or applications in which the timing margin is not so critical. An initial or default frequency of the clock is set. Clock control settings, such as duty cycle, VCO range and gain, etc, are also initialized and set as some default. Test, such as ABIST, LBIST or other functional tests, are performed on the clocked system and the clock frequency is incrementally increased until the tests fail. Upon failure of the tests, one or more clock control settings are adjusted and the tests are run again at the failing frequency. If the tests successfully complete, indicating no errors, the clock frequency is incremented again until the test fail. Again, the clock control settings are adjusted and the tests are repeated at increasing frequency until failure of the tests or until a desired timing margin is reached.
摘要翻译：公开了一种调节计时系统（如数字计算机或存储器控制器）的操作或定时裕度的方法。该方法可以在每个初始程序加载时自动发生，或者可以针对频率，操作电压或其中定时裕度不那么关键的应用进行手动调整。设置时钟的初始或默认频率。诸如占空比，VCO范围和增益等的时钟控制设置也被初始化并设置为一些默认值。在时钟系统上执行诸如ABIST，LBIST或其他功能测试的测试，并且时钟频率逐渐增加，直到测试失败。测试失败后，调整一个或多个时钟控制设置，并在故障频率下再次运行测试。如果测试成功完成，表明没有错误，则时钟频率再次递增，直到测试失败。再次，时钟控制设置被调整，测试以增加的频率重复，直到测试失败或直到达到期望的时序余量。

8. 发明授权

US07760843B2 High frequency divider state correction circuit 失效
标题翻译：高分频器状态校正电路
公开(公告)号：US07760843B2
公开(公告)日：2010-07-20
申请号：US12187517
申请日：2008-08-07
申请人： David William Boerstler , Eric John Lukes , Hiroki Kihara , James David Strom
发明人： David William Boerstler , Eric John Lukes , Hiroki Kihara , James David Strom
IPC分类号： H03K21/00
CPC分类号： H03K21/406 , G06F7/58
摘要： The present invention provides for a self-correcting state circuit. A first flip flop is configured to receive a clock input and a first data input, and to generate a first output in response to the clock input and the first data input. A second flip flop is coupled to the first flip flop and configured to receive the clock input and to receive the first output as a second data input, and to generate a second output in response to the clock input and the first output. A first correction circuit is coupled to the second flip flop and configured to generate a corrected output. A third flip flop is coupled to the first correction circuit and configured to receive the clock input and to receive the corrected output as a third data input, and to generate a third output in response to the clock input and the third data input.
摘要翻译：本发明提供一种自校正状态电路。第一触发器被配置为接收时钟输入和第一数据输入，并且响应于时钟输入和第一数据输入而产生第一输出。第二触发器耦合到第一触发器并且被配置为接收时钟输入并且接收第一输出作为第二数据输入，并且响应于时钟输入和第一输出而产生第二输出。第一校正电路耦合到第二触发器并且被配置为产生校正输出。第三触发器耦合到第一校正电路并且被配置为接收时钟输入并且接收校正的输出作为第三数据输入，并且响应于时钟输入和第三数据输入而产生第三输出。

9. 发明申请

US20080208541A1 Method and Enhanced Phase Locked Loop Circuits for Implementing Effective Testing 审中-公开
标题翻译：用于实现有效测试的方法和增强型锁相环电路
公开(公告)号：US20080208541A1
公开(公告)日：2008-08-28
申请号：US11870159
申请日：2007-10-10
申请人： Michael David Cesky , James David Strom
发明人： Michael David Cesky , James David Strom
IPC分类号： G06F17/50
CPC分类号： G06F17/5063 , H03L7/18 , H03L7/1974
摘要： A method and enhanced phase-locked loop (PLL) circuit enable effective testing of the PLL, and a design structure on which the subject circuit resides is provided. A phase frequency detector generates a differential signal, receiving a reference signal and a feedback signal of an output signal of the PLL circuit. A charge pump is coupled to the phase frequency detector receiving the differential signal. The charge pump applies either negative or positive charge pulses to a low-pass filter, which generates a tuning voltage input applied to a voltage controlled oscillator. A first divider is coupled to the voltage controlled oscillator receives and divides down the VCO output signal, providing the output signal of the PLL circuit. A second divider receives the output signal of the PLL circuit and provides the feedback signal to the phase frequency detector. The output signal of PLL circuit is applied to a clock distribution.
摘要翻译：一种方法和增强的锁相环（PLL）电路能够有效地测试PLL，并且提供主题电路所在的设计结构。相位频率检测器产生差分信号，接收PLL电路的输出信号的参考信号和反馈信号。电荷泵耦合到接收差分信号的相位频率检测器。电荷泵将负电荷或正电荷脉冲施加到低通滤波器，产生施加到压控振荡器的调谐电压输入。第一分频器耦合到压控振荡器接收并分频VCO输出信号，提供PLL电路的输出信号。第二分频器接收PLL电路的输出信号，并将反馈信号提供给相位频率检测器。 PLL电路的输出信号应用于时钟分配。

10. 发明授权

US06239665B1 Method and apparatus for switching in metal insulator metal capacitors and fet tuning capacitors for low noise oscillators 失效
标题翻译：用于切换金属绝缘体金属电容器和用于低噪声振荡器的电子调谐电容器的方法和装置
公开(公告)号：US06239665B1
公开(公告)日：2001-05-29
申请号：US09432673
申请日：1999-11-02
申请人： James David Strom
发明人： James David Strom
IPC分类号： H03B508
CPC分类号： H03B5/1228 , H03B5/1215 , H03B5/1253 , H03B5/1265 , H03J2200/10
摘要： A method and apparatus are provided for switching in metal insulator metal (MIM) capacitors and field effect transistor (FET) tuning capacitors for oscillator circuits. Apparatus for switching in metal-insulator-metal (MIM) capacitors and field effect transistor (FET) tuning capacitors for oscillator circuits includes a first differential oscillator node and a second differential oscillator node. A plurality of metal-insulator-metal (MIM) capacitors are connected to the first differential oscillator nodes and a plurality of metal-insulator-metal (MIM) capacitors are connected to the second differential oscillator nodes. A respective switching transistor is connected in series with an associated one of the metal-insulator-metal (MIM) capacitors. Each switching transistor receives a decoding input and is arranged for providing an open or a ground connection for the associated one of the metal-insulator-metal (MIM) capacitors. A first field effect transistor (FET) tuning capacitor has a gate connected to the first differential oscillator node. A second field effect transistor (FET) tuning capacitor has a gate connected to the second differential oscillator node. Each of the first field effect transistor (FET) tuning capacitor and the second field effect transistor (FET) tuning capacitor having a source and a drain connected together and a control voltage applied to the connected source and drain for varying tuning capacitance.
摘要翻译：提供了用于切换用于振荡器电路的金属绝缘体金属（MIM）电容器和场效应晶体管（FET）调谐电容器的方法和装置。用于切换用于振荡器电路的金属 - 绝缘体金属（MIM）电容器和场效应晶体管（FET）调谐电容器的装置包括第一差分振荡器节点和第二差分振荡器节点。多个金属绝缘体金属（MIM）电容器连接到第一差分振荡器节点，并且多个金属 - 绝缘体金属（MIM）电容器连接到第二差分振荡器节点。相应的开关晶体管与金属 - 绝缘体 - 金属（MIM）电容器中的相关联的一个串联连接。每个开关晶体管接收解码输入，并且被布置成为金属 - 绝缘体 - 金属（MIM）电容器中相关联的一个提供开路或接地连接。第一场效应晶体管（FET）调谐电容器具有连接到第一差分振荡器节点的栅极。第二场效应晶体管（FET）调谐电容器具有连接到第二差分振荡器节点的栅极。第一场效应晶体管（FET）调谐电容器和具有连接在一起的源极和漏极的第二场效应晶体管（FET）调谐电容器以及施加到所连接的源极和漏极的控制电压用于改变调谐电容。

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