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1. 发明申请

US20060179346A1 Method for checkpointing instruction groups with out-of-order floating point instructions in a multi-threaded processor 失效
公开(公告)号：US20060179346A1
公开(公告)日：2006-08-10
申请号：US11054988
申请日：2005-02-10
申请人： James Bishop , Hung Le , Michael Mack , Jafar Nahidi , Dung Nguyen , Jose Paredes , Scott Swaney , Brian Thompto
发明人： James Bishop , Hung Le , Michael Mack , Jafar Nahidi , Dung Nguyen , Jose Paredes , Scott Swaney , Brian Thompto
IPC分类号： G06F11/00
CPC分类号： G06F11/1407
摘要： A method and apparatus are provided for dispatch group checkpointing in a microprocessor, including provisions for handling partially completed dispatch groups and instructions which modify system coherent state prior to completion. An instruction checkpoint retry mechanism is implemented to recover from soft errors in logic. The processor is able to dispatch fixed point unit (FXU), load/store unit (LSU), and floating point unit (FPU) or vector multimedia extension (VMX) instructions on the same cycle. Store data is written to a store queue when a store instruction finishes executing. The data is held in the store queue until the store instruction is checkpointed, at which point it can be released to the coherently shared level 2 (L2) cache.

2. 发明申请

US20060184768A1 Method and apparatus for dynamic modification of microprocessor instruction group at dispatch 有权
标题翻译：调度微处理器指令组动态修改的方法和装置
公开(公告)号：US20060184768A1
公开(公告)日：2006-08-17
申请号：US11055831
申请日：2005-02-11
申请人： James Bishop , Hung Le , Jafar Nahidi , Dung Nguyen , Brian Thompto
发明人： James Bishop , Hung Le , Jafar Nahidi , Dung Nguyen , Brian Thompto
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/30149 , G06F9/382 , G06F9/3853
摘要： Dynamic reformatting of a dispatch group by selective activation of inactive Start bits of instructions within the dispatch group at the time the instructions are read from the IBUF. The number of instructions in the reformatted dispatch groups can vary from as few as one instruction per group to a maximum number of instructions read from the IBUF per cycle. The reformatted dispatch groupings can be terminated after a single cycle, or they can remain reformatted for as many cycles as desired, depending upon need.
摘要翻译：通过在从IBUF读取指令时选择性地激活调度组内的非活动的开始位指令来动态重新格式化调度组。重新格式化的调度组中的指令数量可以从每组少至一个指令变化到每个周期从IBUF读取的最大指令数。重新格式化的调度分组可以在单个周期之后终止，或者根据需要，它们可以根据需要保持重新格式化多个周期。

3. 发明申请

US20060179207A1 Processor instruction retry recovery 有权
标题翻译：处理器指令重试恢复
公开(公告)号：US20060179207A1
公开(公告)日：2006-08-10
申请号：US11055258
申请日：2005-02-10
申请人： Susan Eisen , Hung Le , Michael Mack , Dung Nguyen , Jose Paredes , Scott Swaney
发明人： Susan Eisen , Hung Le , Michael Mack , Dung Nguyen , Jose Paredes , Scott Swaney
IPC分类号： G06F12/14
CPC分类号： G06F12/0888 , G06F9/30043 , G06F9/3851 , G06F9/3863 , G06F11/1407
摘要： Recovery circuits react to errors in a processor core by waiting for an error-free completion of any pending store-conditional instruction or a cache-inhibited load before ceasing to checkpoint or backup progress of a processor core. Recovery circuits remove the processor core from the logical configuration of the symmetric multiprocessor system, potentially reducing propagation of errors to other parts of the system. The processor core is reset and the checkpointed values may be restored to registers of the processor core. The core processor is allowed not just to resume execution just prior to the instructions that failed to execute correctly the first time, but is allowed to operate in a reduced execution mode for a preprogrammed number of groups. If the preprogrammed number of instruction groups execute without error, the processor core is allowed to resume normal execution.
摘要翻译：恢复电路通过在停止处理器核心的检查点或备份进程之前等待任何挂起的存储条件指令或高速缓存禁止负载的无差错完成来响应处理器内核中的错误。恢复电路将处理器核从对称多处理器系统的逻辑配置中移除，可能会将错误的传播减少到系统的其他部分。处理器内核被复位，检查点值可以恢复到处理器内核的寄存器。允许核心处理器不仅在第一次执行失败的指令之前恢复执行，而且允许以预编程的组数减少执行模式运行。如果指令组的预编程数量无错误地执行，则允许处理器内核恢复正常执行。

4. 发明申请

US20060184946A1 Thread priority method, apparatus, and computer program product for ensuring processing fairness in simultaneous multi-threading microprocessors 失效
标题翻译：线程优先方法，装置和计算机程序产品，用于确保同时多线程微处理器的处理公平性
公开(公告)号：US20060184946A1
公开(公告)日：2006-08-17
申请号：US11055850
申请日：2005-02-11
申请人： James Bishop , Hung Le , Dung Nguyen , Balaram Sinharoy , Brian Thompto , Raymond Yeung
发明人： James Bishop , Hung Le , Dung Nguyen , Balaram Sinharoy , Brian Thompto , Raymond Yeung
IPC分类号： G06F9/46
CPC分类号： G06F9/30101 , G06F9/3834 , G06F9/3851 , G06F9/3861 , G06F9/3885 , G06F9/4818 , G06F9/485
摘要： A method, apparatus, and computer program product are disclosed in a data processing system for ensuring processing fairness in simultaneous multi-threading (SMT) microprocessors that concurrently execute multiple threads during each clock cycle. A clock cycle priority is assigned to a first thread and to a second thread during a standard selection state that lasts for an expected number of clock cycles. The clock cycle priority is assigned according to a standard selection definition during the standard selection state by selecting the first thread to be a primary thread and the second thread to be a secondary thread during the standard selection state. If a condition exists that requires overriding the standard selection definition, an override state is executed during which the standard selection definition is overridden by selecting the second thread to be the primary thread and the first thread to be the secondary thread. The override state is forced to be executed for an override period of time which equals the expected number of clock cycles plus a forced number of clock cycles. The forced number of clock cycles is granted to the first thread in response to the first thread again becoming the primary thread.
摘要翻译：在数据处理系统中公开了一种方法，装置和计算机程序产品，用于确保在每个时钟周期期间同时执行多个线程的同时多线程（SMT）微处理器中的处理公平性。在持续预期数量的时钟周期的标准选择状态期间，将时钟周期优先级分配给第一线程和第二线程。在标准选择状态期间，根据标准选择定义分配时钟周期优先级，通过在标准选择状态期间选择作为主线程的第一线程和第二线程作为次线程。如果存在需要覆盖标准选择定义的条件，则执行超越状态，在该状态期间，通过选择第二个线程作为主线程，并将第一个线程作为次要线程来覆盖标准选择定义。超时状态被强制执行超时时间等于预期的时钟周期数加上强制的时钟周期数。响应于第一个线程再次成为主线程，强制的时钟周期数被授予第一个线程。

5. 发明申请

US20060184767A1 Dynamic recalculation of resource vector at issue queue for steering of dependent instructions 有权
标题翻译：动态重新计算依赖指令转向问题队列中的资源向量
公开(公告)号：US20060184767A1
公开(公告)日：2006-08-17
申请号：US11056691
申请日：2005-02-11
申请人： Hung Le , Dung Nguyen , Brian Thompto , Raymond Yeung
发明人： Hung Le , Dung Nguyen , Brian Thompto , Raymond Yeung
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/3836
摘要： A method and apparatus for steering instructions dynamically, at issue time, so as to maximize the efficiency of use of execution units being shared by multiple threads being processed by an SMT processor. Resource vectors are used at issue time to redirect instructions, from threads being processed simultaneously, to shared resources for which the multiple threads are competing. The existing resource vectors for instructions that are queued for issuance are analyzed and, where appropriate, dynamically recalculated and modified for maximum efficiency.
摘要翻译：一种用于在问题时刻动态地转向指令的方法和装置，以便最大化由SMT处理器处理的多个线程共享的执行单元的使用效率。在发布时使用资源向量将来自正在被处理的线程的指令重定向到多个线程正在竞争的共享资源。分析用于发行排队的指令的现有资源向量，并在适当情况下动态重新计算和修改以最大限度地提高效率。

6. 发明申请

US20080091928A1 Branch lookahead prefetch for microprocessors 有权
标题翻译：用于微处理器的分支前瞻预取
公开(公告)号：US20080091928A1
公开(公告)日：2008-04-17
申请号：US11953799
申请日：2007-12-10
申请人： Richard Eickemeyer , Hung Le , Dung Nguyen , Benjamin Stolt , Brian Thompto
发明人： Richard Eickemeyer , Hung Le , Dung Nguyen , Benjamin Stolt , Brian Thompto
IPC分类号： G06F9/38
CPC分类号： G06F9/3842 , G06F9/3861
摘要： A method of handling program instructions in a microprocessor which reduces delays associated with mispredicted branch instructions, by detecting the occurrence of a stall condition during execution of the program instructions, speculatively executing one or more pending instructions which include at least one branch instruction during the stall condition, and determining the validity of data utilized by the speculative execution. Dispatch logic determines the validity of the data by marking one or more registers of an instruction dispatch unit to indicate which results of the pending instructions are invalid. The speculative execution of instructions can occur across multiple pipeline stages of the microprocessor, and the validity of the data is tracked during their execution in the multiple pipeline stages while monitoring a dependency of the speculatively executed instructions relative to one another during their execution in the multiple pipeline stages.
摘要翻译：一种处理微处理器中的程序指令的方法，其通过在执行程序指令期间检测到失速状态的发生来减少与错误预测的分支指令相关联的延迟，推测性地执行一个或多个未决指令，其中包括在失速期间包括至少一个分支指令条件，并确定投机执行使用的数据的有效性。调度逻辑通过标记指令调度单元的一个或多个寄存器来指示待处理指令的哪些结果无效来确定数据的有效性。指令的推测执行可以在微处理器的多个流水线阶段发生，并且在多个流水线阶段的执行期间跟踪数据的有效性，同时在多个流水线阶段的执行期间监视推测性执行的指令相对于彼此的依赖性流水线阶段

7. 发明申请

US20060149935A1 Load lookahead prefetch for microprocessors 失效
公开(公告)号：US20060149935A1
公开(公告)日：2006-07-06
申请号：US11016236
申请日：2004-12-17
申请人： Richard Eickemeyer , Hung Le , Dung Nguyen , Benjamin Stolt , Brian Thompto
发明人： Richard Eickemeyer , Hung Le , Dung Nguyen , Benjamin Stolt , Brian Thompto
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3804 , G06F9/383 , G06F9/3838 , G06F9/3851
摘要： The present invention allows a microprocessor to identify and speculatively execute future load instructions during a stall condition. This allows forward progress to be made through the instruction stream during the stall condition which would otherwise cause the microprocessor or thread of execution to be idle. The data for such future load instructions can be prefetched from a distant cache or main memory such that when the load instruction is re-executed (non speculative executed) after the stall condition expires, its data will reside either in the L1 cache, or will be enroute to the processor, resulting in a reduced execution latency. When an extended stall condition is detected, load lookahead prefetch is started allowing speculative execution of instructions that would normally have been stalled. In this speculative mode, instruction operands may be invalid due to source loads that miss the L1 cache, facilities not available in speculative execution mode, or due to speculative instruction results that are not available via forwarding and are not written to the architected registers. A set of status bits are used to dynamically keep track of the dependencies between instructions in the pipeline and a bit vector tracks invalid architected facilities with respect to the speculative instruction stream. Both sources of information are used to identify load instructions with valid operands for calculating the load address. If the operands are valid, then a load prefetch operation is started to retrieve data from the cache ahead of time such that it can be available for the load instruction when it is non-speculatively executed.

8. 发明申请

US20080077776A1 Load Lookahead Prefetch for Microprocessors 有权
标题翻译：加载用于微处理器的前瞻预取
公开(公告)号：US20080077776A1
公开(公告)日：2008-03-27
申请号：US11950495
申请日：2007-12-05
申请人： Richard Eickemeyer , Hung Le , Dung Nguyen , Benjamin Stolt , Brian Thompto
发明人： Richard Eickemeyer , Hung Le , Dung Nguyen , Benjamin Stolt , Brian Thompto
IPC分类号： G06F9/38
CPC分类号： G06F9/3842 , G06F9/3804 , G06F9/383 , G06F9/3838 , G06F9/3851
摘要： The present invention allows a microprocessor to identify and speculatively execute future load instructions during a stall condition. This allows forward progress to be made through the instruction stream during the stall condition which would otherwise cause the microprocessor or thread of execution to be idle. The data for such future load instructions can be prefetched from a distant cache or main memory such that when the load instruction is re-executed (non speculative executed) after the stall condition expires, its data will reside either in the L1 cache, or will be enroute to the processor, resulting in a reduced execution latency. When an extended stall condition is detected, load lookahead prefetch is started allowing speculative execution of instructions that would normally have been stalled. In this speculative mode, instruction operands may be invalid due to source loads that miss the L1 cache, facilities not available in speculative execution mode, or due to speculative instruction results that are not available via forwarding and are not written to the architected registers. A set of status bits are used to dynamically keep track of the dependencies between instructions in the pipeline and a bit vector tracks invalid architected facilities with respect to the speculative instruction stream. Both sources of information are used to identify load instructions with valid operands for calculating the load address. If the operands are valid, then a load prefetch operation is started to retrieve data from the cache ahead of time such that it can be available for the load instruction when it is non-speculatively executed.
摘要翻译：本发明允许微处理器在失速状态期间识别并推测性地执行未来的加载指令。这允许在停顿条件期间通过指令流进行正向进展，否则将导致微处理器或执行线程空闲。可以从远程高速缓存或主存储器预取这样的未来加载指令的数据，使得当停止条件到期之后，当加载指令被重新执行（不推测执行）时，其数据将驻留在L1高速缓存中，或者将进入处理器，导致执行时间缩短。当检测到扩展失速条件时，启动加载前瞻预取，允许推测执行通常已经停止的指令。在这种推测模式中，由于缺少L1高速缓存的源负载，设备在推测执行模式下不可用的设备，或由于不能通过转发而不能使用并且未写入到架构化寄存器的推测性指令结果，指令操作数可能无效。一组状态位用于动态地跟踪流水线中的指令之间的依赖关系，并且位向量相对于推测性指令流跟踪无效的架构设施。两个信息来源用于识别加载指令，其中包含用于计算加载地址的有效操作数。如果操作数有效，则启动加载预取操作以提前从高速缓存中检索数据，使得当非推测性地执行加载指令时，可以对加载指令可用。

9. 发明申请

US20060149934A1 Using a modified value GPR to enhance lookahead prefetch 失效
标题翻译：使用修改值GPR来增强前瞻预取
公开(公告)号：US20060149934A1
公开(公告)日：2006-07-06
申请号：US11016206
申请日：2004-12-17
申请人： Richard Eickemever , Hung Le , Dung Nguyen , Benjamin Stolt , Brian Thompto
发明人： Richard Eickemever , Hung Le , Dung Nguyen , Benjamin Stolt , Brian Thompto
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3804 , G06F9/383 , G06F9/3838
摘要： The present invention allows a microprocessor to identify and speculatively execute future instructions during a stall condition. This allows forward progress to be made through the instruction stream during the stall condition which would otherwise cause the microprocessor or thread of execution to be idle. The execution of such future instructions can initiate a prefetch of data or instructions from a distant cache or main memory, or otherwise make forward progress through the instruction stream. In this manner, when the instructions are re-executed (non speculatively executed) after the stall condition expires, they will execute with a reduced execution latency; e.g. by accessing data prefetched into the L1 cache, or enroute to the processor, or by executing the target instructions following a speculatively resolved mispredicted branch. In speculative mode, instruction operands may be invalid due to source loads that miss the L1 cache, facilities not available in speculative execution mode, or due to speculative instruction results that are not available. Dependency and dirty (i.e. invalid result) bits are tracked and used to determine which speculative instructions are valid for execution. A modified value register storage and bit vector are used to improve the availability of speculative results that would otherwise be discarded once they leave the execution pipeline because they cannot be written to the architected registers. The modified general purpose registers are used to store speculative results when the corresponding instruction reaches writeback and the modified bit vector tracks the results that have been stored there. Younger speculative instructions that do not bypass directly from older instructions will then use this modified data when the corresponding bit in the modified bit vector indicates the data has been modified. Otherwise, data from the architected registers will be used.
摘要翻译：本发明允许微处理器在失速状态期间识别和推测地执行未来的指令。这允许在停顿条件期间通过指令流进行正向进展，否则将导致微处理器或执行线程空闲。这样的未来指令的执行可以启动来自远程高速缓存或主存储器的数据或指令的预取，或以其他方式通过指令流进行进展。以这种方式，当在停止条件到期之后重新执行（不推测地执行）指令时，它们将以降低的执行延迟执行; 例如通过访问预取到L1高速缓存中的数据，或者进入处理器，或通过在推测性地解决的误预测分支之后执行目标指令。在推测模式中，由于缺少L1缓存的源加载，在推测执行模式下不可用的设备，或由于不可用的推测指令结果，指令操作数可能无效。跟踪依赖关系和脏（即无效结果）位，并用于确定哪些推测指令对执行有效。改进的值寄存器存储和位向量被用于提高推测结果的可用性，否则，由于不能将其写入到架构化的寄存器，否则将抛弃执行流水线。修改后的通用寄存器用于在对应指令到达回写时存储推测结果，修改后的位向量跟踪存储在其中的结果。当修改的位向量中的相应位指示数据已被修改时，不直接从旧指令旁路的较小的推测指令将使用该修改的数据。否则，将使用来自架构化寄存器的数据。

10. 发明申请

US20060149933A1 Branch lookahead prefetch for microprocessors 失效
标题翻译：用于微处理器的分支前瞻预取
公开(公告)号：US20060149933A1
公开(公告)日：2006-07-06
申请号：US11016200
申请日：2004-12-17
申请人： Richard Eickemeyer , Hung Le , Dung Nguyen , Benjamin Stolt , Brian Thompto
发明人： Richard Eickemeyer , Hung Le , Dung Nguyen , Benjamin Stolt , Brian Thompto
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3861
摘要： A method of handling program instructions in a microprocessor which reduces delays associated with mispredicted branch instructions, by detecting the occurrence of a stall condition during execution of the program instructions, speculatively executing one or more pending instructions which include at least one branch instruction during the stall condition, and determining the validity of data utilized by the speculative execution. In particular, the method can detect a load instruction miss which results in the stall condition. Dispatch logic determines the validity of the data by marking one or more registers of an instruction dispatch unit to indicate which results of the pending instructions are invalid. The speculative execution of instructions can occur across multiple pipeline stages of the microprocessor, and the validity of the data is tracked during their execution in the multiple pipeline stages while monitoring a dependency of the speculatively executed instructions relative to one another during their execution in the multiple pipeline stages. A branch prediction unit predicts a path of the branch instruction prior to detection of the stall condition, and fetches speculative instructions from the predicted path into an instruction queue. If the speculative execution of the branch instruction indicates it was mispredicted, the speculative instructions are flushed from the pipeline and instruction queue, and the branch prediction information is updated based on results of the speculative execution of the branch instruction. The speculative execution of the instructions occurs without altering any architected facilities of the microprocessor.
摘要翻译：一种处理微处理器中的程序指令的方法，其通过在执行程序指令期间检测到失速状态的发生来减少与错误预测的分支指令相关联的延迟，推测性地执行一个或多个未决指令，其中包括在失速期间包括至少一个分支指令条件，并确定投机执行使用的数据的有效性。特别地，该方法可以检测到导致失速状态的加载指令未命中。调度逻辑通过标记指令调度单元的一个或多个寄存器来指示待处理指令的哪些结果无效来确定数据的有效性。指令的推测执行可以在微处理器的多个流水线阶段发生，并且在多个流水线阶段的执行期间跟踪数据的有效性，同时在多个流水线阶段的执行期间监视推测性执行的指令相对于彼此的依赖性流水线阶段分支预测单元在检测到停顿条件之前预测分支指令的路径，并且从预测路径获取推测指令到指令队列中。如果分支指令的推测执行指示它被错误预测，则从流水线和指令队列刷新推测指令，并且基于分支指令的推测执行的结果更新分支预测信息。指令的推测执行不会改变微处理器的任何架构设计。

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