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1. 发明授权

US06426536B1 Double layer perovskite oxide electrodes 失效
标题翻译：双层钙钛矿氧化物电极
公开(公告)号：US06426536B1
公开(公告)日：2002-07-30
申请号：US09835509
申请日：2001-04-16
申请人： James A. Misewich , Ramamoorthy Ramesh , Alejandro G. Schrott
发明人： James A. Misewich , Ramamoorthy Ramesh , Alejandro G. Schrott
IPC分类号： H01L2976
CPC分类号： H01L49/003
摘要： A method for constructing oxide electrodes for use in an OxFET device is disclosed. The electrodes are formed by first depositing a double layer of conducting perovskite oxides onto an insulating oxide substrate. A resist pattern with the electrode configuration is then defined over the double layer by means of conventional lithography. The top oxide layer is ion milled to a depth preferably beyond the conducting oxide interface, but without reaching the substrate. Chemical etching or RIE is used to remove the part of the lower conductive oxide layer exposed by ion milling without damaging the substrate. Source and drain electrodes are thereby defined, which can be then be used as buried contacts for other perovskites that tend to react with metals. Also disclosed is a field effect transistor structure which includes these source and drain electrodes in a buried channel configuration.
摘要翻译：公开了一种用于构造用于OxFET器件的氧化物电极的方法。电极通过首先将双层导电钙钛矿氧化物沉积到绝缘氧化物基底上而形成。然后通过常规光刻在双层上限定具有电极构型的抗蚀剂图案。将顶部氧化物层离子研磨至优选超过导电氧化物界面的深度，但不到达衬底。使用化学蚀刻或RIE来去除通过离子研磨暴露的下部导电氧化物层的一部分而不损坏衬底。源电极和漏极电极由此被定义，然后可以将其用作倾向于与金属反应的其他钙钛矿的掩埋触点。还公开了一种场效应晶体管结构，其包括处于掩埋沟道构型的这些源极和漏极。

2. 发明授权

US06350622B2 Process for fabrication of an all-epitaxial-oxide transistor 有权
标题翻译：制造全外延氧化物晶体管的工艺
公开(公告)号：US06350622B2
公开(公告)日：2002-02-26
申请号：US09768172
申请日：2001-01-24
申请人： James A. Misewich , Alejandro G. Schrott
发明人： James A. Misewich , Alejandro G. Schrott
IPC分类号： H01L2100
CPC分类号： H01L49/003
摘要： A method and structure of forming an integrated circuit chip having a transistor includes forming a conductive oxide layer, forming a Mott transition oxide layer over the conductive oxide layer and forming an insulative oxide layer over the Mott transition oxide layer.
摘要翻译：形成具有晶体管的集成电路芯片的方法和结构包括形成导电氧化物层，在导电氧化物层上形成Mott过渡氧化物层，并在Mott过渡氧化物层上形成绝缘氧化物层。

3. 发明授权

US06479847B2 Method for complementary oxide transistor fabrication 失效
标题翻译：互补氧化物晶体管制造方法
公开(公告)号：US06479847B2
公开(公告)日：2002-11-12
申请号：US09306509
申请日：1999-05-07
申请人： James A. Misewich , Alejandro G. Schrott , Bruce A. Scott
发明人： James A. Misewich , Alejandro G. Schrott , Bruce A. Scott
IPC分类号： H01L2975
CPC分类号： H01L49/003 , H01L21/8238
摘要： A method of manufacturing an integrated circuit device includes forming a laminated structure having a first side and a second side, the first side includes a first type Mott channel layer and the second side includes a second type Mott channel layer. A first source region and a first drain region is formed on the first side, a second source region and a second drain region is formed on the second side, a first gate region is formed on the second side, opposite the first source region and the first drain region and a second gate region is formed on the first side, opposite the second source region and the second drain region. The first source, the first drain and the first gate comprise a first type field effect transistor and the second source, the second drain and the second gate comprise a second type field effect transistor.
摘要翻译：一种集成电路器件的制造方法包括：形成具有第一侧面和第二侧面的层叠结构体，第一面包括第一类型的Mott沟道层，第二面包括第二类型的Mott沟道层。第一源区和第一漏区形成在第一侧上，第二源区和第二漏区形成在第二侧上，第一栅极区形成在与第一源区相对的第二侧上，第一漏区和第二栅区形成在与第二源区和第二漏区相对的第一侧上。第一源极，第一漏极和第一栅极包括第一类型场效应晶体管，第二源极，第二漏极和第二栅极包括第二类型场效应晶体管。

4. 发明授权

US06555393B2 Process for fabricating a field-effect transistor with a buried Mott material oxide channel 失效
标题翻译：用埋置的Mott材料氧化物沟道制造场效晶体管的工艺
公开(公告)号：US06555393B2
公开(公告)日：2003-04-29
申请号：US09938392
申请日：2001-08-24
申请人： Alejandro G. Schrott , James A. Misewich , Bruce A. Scott
发明人： Alejandro G. Schrott , James A. Misewich , Bruce A. Scott
IPC分类号： H01L2100
CPC分类号： H01L49/003
摘要： A structure and method of forming an integrated circuit (e.g., field effect transistor) having a buried Mott-insulated oxide channel includes depositing source and drain electrodes over a substrate forming a Mott transition channel layer over the substrate and electrodes, forming an insulator layer over the Mott transition channel layer, forming source and drain contacts through the insulator layer (such that the source and drain contacts are electrically connected to the Mott transition channel layer) and forming a gate electrode over the insulator layer between the source and drain contacts.
摘要翻译：形成具有掩埋的Mott绝缘氧化物沟道的集成电路（例如，场效应晶体管）的结构和方法包括在衬底上形成基底和电极上形成Mott过渡沟道层的衬底上沉积源极和漏极，形成绝缘体层 Mott过渡沟道层，通过绝缘体层形成源极和漏极触点（使得源极和漏极触点电连接到Mott过渡沟道层），并在源极和漏极触点之间的绝缘体层上形成栅电极。

5. 发明授权

US06333543B1 Field-effect transistor with a buried mott material oxide channel 失效
标题翻译：场效应晶体管与掩埋火炬材料氧化物通道
公开(公告)号：US06333543B1
公开(公告)日：2001-12-25
申请号：US09268633
申请日：1999-03-16
申请人： Alejandro G. Schrott , James A. Misewich , Bruce A. Scott
发明人： Alejandro G. Schrott , James A. Misewich , Bruce A. Scott
IPC分类号： H01L1912
CPC分类号： H01L49/003
摘要： A structure and method of forming an integrated circuit (e.g., field effect transistor) having a buried Mott-insulated oxide channel includes depositing source and drain electrodes over a substrate forming a Mott transition channel layer over the substrate and electrodes, forming an insulator layer over the Mott transition channel layer, forming source and drain contacts through the insulator layer (such that the source and drain contacts are electrically connected to the Mott transition channel layer) and forming a gate electrode over the insulator layer between the source and drain contacts.
摘要翻译：形成具有掩埋的Mott绝缘氧化物沟道的集成电路（例如，场效应晶体管）的结构和方法包括在衬底上形成基底和电极上形成Mott过渡沟道层的衬底上沉积源极和漏极，形成绝缘体层 Mott过渡沟道层，通过绝缘体层形成源极和漏极触点（使得源极和漏极触点电连接到Mott过渡沟道层），并在源极和漏极触点之间的绝缘体层上形成栅电极。

6. 发明授权

US06259114B1 Process for fabrication of an all-epitaxial-oxide transistor 失效
标题翻译：制造全外延氧化物晶体管的工艺
公开(公告)号：US06259114B1
公开(公告)日：2001-07-10
申请号：US09306635
申请日：1999-05-07
申请人： James A. Misewich , Alejandro G. Schrott
发明人： James A. Misewich , Alejandro G. Schrott
IPC分类号： H01L2912
CPC分类号： H01L49/003
摘要： A method and structure of forming an integrated circuit chip having a transistor includes forming a conductive oxide layer, forming a Mott transition oxide layer over the conductive oxide layer and forming an insulative oxide layer over the Mott transition oxide layer.
摘要翻译：形成具有晶体管的集成电路芯片的方法和结构包括形成导电氧化物层，在导电氧化物层上形成Mott过渡氧化物层，并在Mott过渡氧化物层上形成绝缘氧化物层。

7. 发明授权

US09111609B2 Concentric phase change memory element 有权
标题翻译：同心相变存储元件
公开(公告)号：US09111609B2
公开(公告)日：2015-08-18
申请号：US13364727
申请日：2012-02-02
申请人： Thomas D. Happ , Alejandro G. Schrott
发明人： Thomas D. Happ , Alejandro G. Schrott
IPC分类号： H01L21/00 , G11C13/00 , H01L45/00 , G11C11/56
CPC分类号： G11C13/0004 , G11C11/5678 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/148 , H01L45/1616 , H01L45/165 , H01L45/1675 , H01L45/1683
摘要： The present invention in one embodiment provides a memory device including a first electrode; a second electrode; and a memory cell positioned between the first electrode and the second electrode, the memory cell including a core of a first phase change material and a cladding of a second phase change material, wherein the first phase change material has a lower crystallization temperature than the second phase change material. The present invention also provides methods of forming the above described memory device.
摘要翻译：本发明在一个实施例中提供了一种包括第一电极的存储器件; 第二电极; 以及位于所述第一电极和所述第二电极之间的存储单元，所述存储单元包括第一相变材料的芯和第二相变材料的包层，其中所述第一相变材料具有比所述第二相变材料低的结晶温度相变材料本发明还提供了形成上述存储器件的方法。

8. 发明授权

US08559217B2 Phase change material cell with stress inducer liner 有权
标题翻译：相变材料电池与应力诱导衬管
公开(公告)号：US08559217B2
公开(公告)日：2013-10-15
申请号：US12964980
申请日：2010-12-10
申请人： Catherine A. Dubourdieu , Martin M. Frank , Bipin Rajendran , Alejandro G. Schrott
发明人： Catherine A. Dubourdieu , Martin M. Frank , Bipin Rajendran , Alejandro G. Schrott
IPC分类号： G11C11/00
CPC分类号： H01L45/1608 , G11C11/22 , G11C13/0004 , G11C13/0069 , G11C2013/0095 , H01L45/06 , H01L45/12 , H01L45/1233 , H01L45/143 , H01L45/144
摘要： An example embodiment disclosed is a phase change memory cell. The memory cell includes a phase change material and a transducer positioned proximate the phase change material. The phase change material is switchable between at least an amorphous state and a crystalline state. The transducer is configured to activate when the phase change material is changed from the amorphous state to the crystalline state. In a particular embodiment, the transducer is ferroelectric material.
摘要翻译：所公开的示例实施例是相变存储单元。存储单元包括相变材料和位于相变材料附近的换能器。相变材料可在至少非晶状态和结晶状态之间切换。换能器被配置为当相变材料从非晶状态转变为结晶状态时激活。在特定实施例中，换能器是铁电材料。

9. 发明授权

US08383501B2 Vertical field effect transistor arrays and methods for fabrication thereof 有权
标题翻译：垂直场效应晶体管阵列及其制造方法
公开(公告)号：US08383501B2
公开(公告)日：2013-02-26
申请号：US13185055
申请日：2011-07-18
申请人： Matthew J. Breitwisch , Chung H. Lam , Alejandro G. Schrott
发明人： Matthew J. Breitwisch , Chung H. Lam , Alejandro G. Schrott
IPC分类号： H01L21/28
CPC分类号： H01L21/823487 , H01L27/088
摘要： Vertical field effect transistor semiconductor structures and methods for fabrication of the vertical field effect transistor semiconductor structures provide an array of semiconductor pillars. Each vertical portion of each semiconductor pillar in the array of semiconductor pillars has a linewidth greater than a separation distance to an adjacent semiconductor pillar. Alternatively, the array may comprise semiconductor pillars with different linewidths, optionally within the context of the foregoing linewidth and separation distance limitations. A method for fabricating the array of semiconductor pillars uses a minimally photolithographically dimensioned pillar mask layer that is annularly augmented with at least one spacer layer prior to being used as an etch mask.
摘要翻译：垂直场效应晶体管半导体结构和用于制造垂直场效应晶体管半导体结构的方法提供半导体柱阵列。半导体柱阵列中的每个半导体柱的每个垂直部分具有大于与相邻半导体柱的间隔距离的线宽。或者，阵列可以包括具有不同线宽的半导体柱，任选地在上述线宽和间隔距离限制的上下文中。用于制造半导体柱阵列的方法使用最小光刻尺寸的柱掩模层，其在被用作蚀刻掩模之前用至少一个间隔层环形增强。

10. 发明申请

US20130001500A1 PORE PHASE CHANGE MATERIAL CELL FABRICATED FROM RECESSED PILLAR 有权
公开(公告)号：US20130001500A1
公开(公告)日：2013-01-03
申请号：US13612552
申请日：2012-09-12
申请人： Alejandro G. Schrott , Chung H. Lam , Eric A. Joseph , Matthew J. Breitwisch , Roger W. Cheek
发明人： Alejandro G. Schrott , Chung H. Lam , Eric A. Joseph , Matthew J. Breitwisch , Roger W. Cheek
IPC分类号： H01L45/00
CPC分类号： H01L45/1625 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/148 , H01L45/1616 , H01L45/165 , H01L45/1666
摘要： A method of manufacturing an electrode is provided that includes providing a pillar of a first phase change material atop a conductive structure of a dielectric layer; or the inverted structure; forming an insulating material atop dielectric layer and adjacent the pillar, wherein an upper surface of the first insulating material is coplanar with an upper surface of the pillar; recessing the upper surface of the pillar below the upper surface of the insulating material to provide a recessed cavity; and forming a second phase change material atop the recessed cavity and the upper surface of the insulating material, wherein the second phase change material has a greater phase resistivity than the first phase change material.

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