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1. 发明授权

US08362938B2 Analog digital converting device 有权
标题翻译：模拟数字转换装置
公开(公告)号：US08362938B2
公开(公告)日：2013-01-29
申请号：US12982531
申请日：2010-12-30
申请人： Young Kyun Cho , Young-deuk Jeon , Jaewon Nam , Jong-Kee Kwon
发明人： Young Kyun Cho , Young-deuk Jeon , Jaewon Nam , Jong-Kee Kwon
IPC分类号： H03M1/12
CPC分类号： H03M1/145 , H03M1/365 , H03M1/468
摘要： Provided is an analog digital converting device which consumes a low power and guarantees fast operation characteristic. The analog digital converting device includes a sub-ADC and a successive approximation ADC. The sub-ADC converts an external analog signal into a first digital signal by using first and second reference voltages. The successive approximation ADC comprises a plurality of bit streams, and converts the external analog signal into a second digital signal according to a successive approximation operation using the first and second reference voltages. The successive approximation ADC receives the first digital signal, and converts the second digital signal in a state where one of the first and second reference voltages has been applied to the bit streams based on the first digital signal.
摘要翻译：提供了一种消耗低功耗并保证快速操作特性的模拟数字转换装置。模拟数字转换装置包括子ADC和逐次逼近ADC。子ADC通过使用第一和第二参考电压将外部模拟信号转换为第一数字信号。逐次逼近ADC包括多个比特流，并且根据使用第一和第二参考电压的逐次逼近操作将外部模拟信号转换为第二数字信号。逐次逼近ADC接收第一数字信号，并且在第一和第二参考电压中的一个被基于第一数字信号施加到比特流的状态下转换第二数字信号。

2. 发明申请

US20120062406A1 ANALOG DIGITAL CONVERTING DEVICE 有权
标题翻译：模拟数字转换器件
公开(公告)号：US20120062406A1
公开(公告)日：2012-03-15
申请号：US12982531
申请日：2010-12-30
申请人： Young Kyun Cho , Young-deuk Jeon , Jaewon Nam , Jong-Kee Kwon
发明人： Young Kyun Cho , Young-deuk Jeon , Jaewon Nam , Jong-Kee Kwon
IPC分类号： H03M1/36 , H03M1/12
CPC分类号： H03M1/145 , H03M1/365 , H03M1/468
摘要： Provided is an analog digital converting device which consumes a low power and guarantees fast operation characteristic. The analog digital converting device includes a sub-ADC and a successive approximation ADC. The sub-ADC converts an external analog signal into a first digital signal by using first and second reference voltages. The successive approximation ADC comprises a plurality of bit streams, and converts the external analog signal into a second digital signal according to a successive approximation operation using the first and second reference voltages. The successive approximation ADC receives the first digital signal, and converts the second digital signal in a state where one of the first and second reference voltages has been applied to the bit streams based on the first digital signal.
摘要翻译：提供了一种消耗低功耗并保证快速操作特性的模拟数字转换装置。模拟数字转换装置包括子ADC和逐次逼近ADC。子ADC通过使用第一和第二参考电压将外部模拟信号转换为第一数字信号。逐次逼近ADC包括多个比特流，并且根据使用第一和第二参考电压的逐次逼近操作将外部模拟信号转换为第二数字信号。逐次逼近ADC接收第一数字信号，并且在第一和第二参考电压中的一个被基于第一数字信号施加到比特流的状态下转换第二数字信号。

3. 发明申请

US20120146821A1 PIPELINED ANALOG DIGITAL CONVERTOR 有权
标题翻译：管道模拟数字转换器
公开(公告)号：US20120146821A1
公开(公告)日：2012-06-14
申请号：US13309872
申请日：2011-12-02
申请人： Jaewon NAM , Young-deuk Jeon , Young Kyun Cho , Jong-Kee Kwon
发明人： Jaewon NAM , Young-deuk Jeon , Young Kyun Cho , Jong-Kee Kwon
IPC分类号： H03M1/12 , H03M1/06
CPC分类号： H03M1/069 , H03M1/168
摘要： Disclosed is a pipelined analog-to-digital converter which includes a digital correction circuit configured to improve the complexity of a logic circuit for dividing a correction period and a no-correction period of a digital output. The pipelined analog-to-digital converter performs a logic correction operation via binary shifting at data error correction. Accordingly, although the resolution increases, it is possible to reduce the complexity and area of a logic circuit.
摘要翻译：公开了一种流水线模数转换器，其包括数字校正电路，其被配置为提高用于分割校正周期和数字输出的无校正周期的逻辑电路的复杂度。流水线模数转换器通过数据纠错的二进制移位执行逻辑校正操作。因此，虽然分辨率增加，但是可以降低逻辑电路的复杂性和面积。

4. 发明申请

US20120146820A1 PIPELINED ANALOG DIGITAL CONVERTOR 有权
标题翻译：管道模拟数字转换器
公开(公告)号：US20120146820A1
公开(公告)日：2012-06-14
申请号：US13243629
申请日：2011-09-23
申请人： Jaewon NAM , Young-deuk Jeon , Young Kyun Cho , Jong-Kee Kwon
发明人： Jaewon NAM , Young-deuk Jeon , Young Kyun Cho , Jong-Kee Kwon
IPC分类号： H03M1/06 , H03M1/12
CPC分类号： H03M1/069 , H03M1/168
摘要： Disclosed is a pipelined analog-to-digital converter which includes a digital correction circuit configured to measure and correct a pipelined conversion stage gain error and an offset error due to a finite voltage gain operational amplifier and capacitor mismatch. The pipelined analog-to-digital converter includes a pipelined conversion stage error measuring and correcting circuit measuring and correcting an error generated from an conversion stage, so that an error of a conversion stage is minimized and a chip realization area and power consumption are reduced.
摘要翻译：公开了一种流水线模数转换器，其包括数字校正电路，其被配置为测量和校正流水线转换级增益误差以及由于有限电压增益运算放大器和电容器失配引起的偏移误差。流水线模数转换器包括流水线转换级误差测量和校正电路，测量和校正从转换级产生的误差，使得转换级的误差最小化，并且芯片实现面积和功耗降低。

5. 发明授权

US08564469B2 Pipelined analog digital convertor 有权
标题翻译：流水线模拟数字转换器
公开(公告)号：US08564469B2
公开(公告)日：2013-10-22
申请号：US13309872
申请日：2011-12-02
申请人： Jaewon Nam , Young-deuk Jeon , Young Kyun Cho , Jong-Kee Kwon
发明人： Jaewon Nam , Young-deuk Jeon , Young Kyun Cho , Jong-Kee Kwon
IPC分类号： H03M1/38
CPC分类号： H03M1/069 , H03M1/168
摘要： A pipelined analog-to-digital converter includes a digital correction circuit configured to improve the complexity of a logic circuit for dividing a correction period and a no-correction period of a digital output. The pipelined analog-to-digital converter performs a logic correction operation via binary shifting at data error correction. Accordingly, although the resolution increases, it is possible to reduce the complexity and area of a logic circuit.
摘要翻译：流水线模数转换器包括数字校正电路，其被配置为提高用于划分校正周期和数字输出的无校正周期的逻辑电路的复杂度。流水线模数转换器通过数据纠错的二进制移位执行逻辑校正操作。因此，虽然分辨率增加，但是可以降低逻辑电路的复杂性和面积。

6. 发明授权

US08531328B2 Analog digital converter 有权
标题翻译：模拟数字转换器
公开(公告)号：US08531328B2
公开(公告)日：2013-09-10
申请号：US13243267
申请日：2011-09-23
申请人： Young-deuk Jeon , Young Kyun Cho , Jaewon Nam , Jong-Kee Kwon
发明人： Young-deuk Jeon , Young Kyun Cho , Jaewon Nam , Jong-Kee Kwon
IPC分类号： H03M1/12
CPC分类号： H03M1/164 , H03M1/468
摘要： Provided is an analog digital converter (ADC). The ADC includes: a capacitor array generating a level voltage; a comparator outputting a compare signal by comparing the level voltage; and a logic circuit determining digital bits of an analog signal based on the compare signal, wherein the logic circuit determines at least one digital bit among digital bits of the analog signal while a sampling operation of the analog signal is performed in the capacitor array.
摘要翻译：提供了一种模拟数字转换器（ADC）。 ADC包括：产生电平电压的电容器阵列; 比较器，通过比较电平电压输出比较信号; 以及逻辑电路，其基于所述比较信号确定模拟信号的数字位，其中所述逻辑电路在所述电容器阵列中执行所述模拟信号的采样操作时，确定所述模拟信号的数字位中的至少一个数字位。

7. 发明授权

US08508392B2 Pipelined analog digital converter 有权
标题翻译：流水线模拟数字转换器
公开(公告)号：US08508392B2
公开(公告)日：2013-08-13
申请号：US13243629
申请日：2011-09-23
申请人： Jaewon Nam , Young-deuk Jeon , Young Kyun Cho , Jong-Kee Kwon
发明人： Jaewon Nam , Young-deuk Jeon , Young Kyun Cho , Jong-Kee Kwon
IPC分类号： H03M1/06
CPC分类号： H03M1/069 , H03M1/168
摘要： Disclosed is a pipelined analog-to-digital converter which includes a digital correction circuit configured to measure and correct a pipelined conversion stage gain error and an offset error due to a finite voltage gain operational amplifier and capacitor mismatch. The pipelined analog-to-digital converter includes a pipelined conversion stage error measuring and correcting circuit measuring and correcting an error generated from an conversion stage, so that an error of a conversion stage is minimized and a chip realization area and power consumption are reduced.
摘要翻译：公开了一种流水线模数转换器，其包括数字校正电路，其被配置为测量和校正流水线转换级增益误差以及由于有限电压增益运算放大器和电容器失配引起的偏移误差。流水线模数转换器包括流水线转换级误差测量和校正电路，测量和校正从转换级产生的误差，使得转换级的误差最小化，并且芯片实现面积和功耗降低。

8. 发明授权

US08164497B2 Pipeline analog-to-digital converter 有权
标题翻译：管道模数转换器
公开(公告)号：US08164497B2
公开(公告)日：2012-04-24
申请号：US12777910
申请日：2010-05-11
申请人： Jae Won Nam , Young Deuk Jeon , Young Kyun Cho , Jong Kee Kwon
发明人： Jae Won Nam , Young Deuk Jeon , Young Kyun Cho , Jong Kee Kwon
IPC分类号： H03M1/00
CPC分类号： H03M1/0836 , H03M1/168
摘要： Provided is a pipeline analog-to-digital converter (ADC) without a front-end sample-and-hold amplifier (SHA). To minimize a sampling error occurring between a flash ADC and a multiplying digital-to-analog converter (MDAC) of a first sub-ranging ADC due to removal of a front-end SHA, a delay time of a preamplifier included in the flash ADC is calculated, and the flash ADC samples an analog input signal later by the delay time than the MDAC. Accordingly, the pipeline ADC can minimize a sampling error without using a front-end SHA, and its chip area and power consumption can be reduced.
摘要翻译：提供了一种没有前端采样和保持放大器（SHA）的流水线模数转换器（ADC）。为了最小化由于去除前端SHA而导致的闪存ADC和第一子范围ADC的乘法数模转换器（MDAC）之间的采样误差，包括在闪存ADC中的前置放大器的延迟时间并且闪速ADC比模拟输入信号稍后采样延迟时间比MDAC。因此，流水线ADC可以在不使用前端SHA的情况下最小化采样误差，并且可以减少其芯片面积和功耗。

9. 发明授权

US08547081B2 Reference voltage supply circuit including a glitch remover 有权
标题翻译：参考电压电路包括毛刺去除器
公开(公告)号：US08547081B2
公开(公告)日：2013-10-01
申请号：US12833841
申请日：2010-07-09
申请人： Young Deuk Jeon , Young Kyun Cho , Jae Won Nam , Jong Kee Kwon
发明人： Young Deuk Jeon , Young Kyun Cho , Jae Won Nam , Jong Kee Kwon
IPC分类号： G05F1/00 , G05F3/16 , G05F3/20
CPC分类号： H03F3/347
摘要： A reference voltage supply circuit is provided. The reference voltage supply circuit includes a first amplifier for amplifying a first input voltage and a fed back first reference voltage, a second amplifier for amplifying a second input voltage and a fed back second reference voltage, a reference voltage generator for generating the first reference voltage and the second reference voltage according to output signals of the first and second amplifiers and feeding the first and second reference voltages back to the first and second amplifiers, and a glitch remover turned on/off according to an input pulse signal to conduct or cut off current flowing between a power supply terminal and the ground.
摘要翻译：提供参考电压供应电路。参考电压供应电路包括用于放大第一输入电压和反馈第一参考电压的第一放大器，用于放大第二输入电压的第二放大器和反馈的第二参考电压;参考电压发生器，用于产生第一参考电压以及根据第一和第二放大器的输出信号的第二参考电压，并将第一和第二参考电压馈送回第一和第二放大器，并且毛刺去除器根据输入脉冲信号导通/截止以导通或切断在电源端子和地之间流动的电流。

10. 发明授权

US08264268B2 Offset-voltage calibration circuit 失效
标题翻译：偏置电压校准电路
公开(公告)号：US08264268B2
公开(公告)日：2012-09-11
申请号：US12843535
申请日：2010-07-26
申请人： Young Kyun Cho , Young Deuk Jeon , Jae Won Nam , Jong Kee Kwon
发明人： Young Kyun Cho , Young Deuk Jeon , Jae Won Nam , Jong Kee Kwon
IPC分类号： H03L5/00
CPC分类号： H03M1/1023 , H03M1/66
摘要： Provided is an offset-voltage calibration circuit. The circuit includes a comparator configured to receive at least two comparison voltages and output a result of a comparison between the comparison voltages, an up/down counter (UDC) configured to output an up-counting or down-counting output signal in response to an output signal of the comparator, and a current digital-to-analog converter (DAC) configured to control the amount of current supplied from a node to which the comparison voltage is applied, in response to the output signal of the UDC and control the magnitude of the comparison voltage.
摘要翻译：提供了一种偏移电压校准电路。所述电路包括比较器，被配置为接收至少两个比较电压并输出所述比较电压之间的比较结果;响应于所述比较电压被配置为输出递增计数或递减计数输出信号的上/下计数器（UDC）比较器的输出信号，以及被配置为响应于UDC的输出信号来控制从施加了比较电压的节点提供的电流量的电流数模转换器（DAC），并且控制幅度的比较电压。

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