专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08604845B2 Triangular wave generator and method generating triangular wave thereof 有权
标题翻译：三角波发生器及其三角波产生方法
公开(公告)号：US08604845B2
公开(公告)日：2013-12-10
申请号：US13488337
申请日：2012-06-04
申请人： Hui Dong Lee , Jaewon Nam , Young Kyun Cho , Jong-Kee Kwon , Yil Suk Yang , Jongdae Kim
发明人： Hui Dong Lee , Jaewon Nam , Young Kyun Cho , Jong-Kee Kwon , Yil Suk Yang , Jongdae Kim
IPC分类号： H03K4/06
CPC分类号： H03K4/501
摘要： Disclosed is a triangular wave generator which includes a square wave signal generating unit configured to output a first signal transitioning to a high level from a low level via an output terminal in response to a first transition of a clock signal and to transition the first signal to a low level from a high level in response to a reset signal; a resistance unit configured to adjust a voltage level of a the square wave signal; and a capacitance unit configured to receive an output signal of the resistance unit to generate a second signal rising to a high level from a low level with a slope, to provide the reset signal to the square wave signal generating unit, and to output a triangular signal by falling the second signal to a low level from a high level with a slope.
摘要翻译：公开了一种三角波发生器，其包括方波信号生成单元，其被配置为响应于时钟信号的第一转换，经由输出端子输出从低电平转换到高电平的第一信号，并且将第一信号转换为响应于复位信号从高电平的低电平; 电阻单元，被配置为调整所述方波信号的电压电平; 以及电容单元，被配置为接收电阻单元的输出信号，以产生从具有斜率的低电平上升到高电平的第二信号，以将复位信号提供给方波信号生成单元，并输出三角形通过从具有斜率的高电平将第二信号降低到低电平来产生信号。

2. 发明授权

US09490734B2 Motor control device and method of controlling the same 有权
标题翻译：电机控制装置及其控制方法
公开(公告)号：US09490734B2
公开(公告)日：2016-11-08
申请号：US13443823
申请日：2012-04-10
申请人： Jaewon Nam , Young Kyun Cho , Hui Dong Lee , Yil Suk Yang , Jong-Kee Kwon , Jongdae Kim
发明人： Jaewon Nam , Young Kyun Cho , Hui Dong Lee , Yil Suk Yang , Jong-Kee Kwon , Jongdae Kim
IPC分类号： H02P6/18 , H02P6/10 , H02P6/20 , H02P6/08
CPC分类号： H02P6/182 , H02P6/085 , H02P6/10 , H02P6/18 , H02P6/21 , H02P2209/07
摘要： A motor control device including a preprocessing portion calculating a counter electromotive force using an analog operation is provided. The motor control device may include an offset compensation portion and a counter electromotive force measuring portion. The offset compensation portion receives a three-phase current signal from the motor and compensates an offset of the three-phase current signal. The counter electromotive force measuring portion receives the compensated current signal and a three-phase voltage signal from the motor and calculates the received current signal and the received voltage signal using an analog operation to provide the calculated result.
摘要翻译：提供了一种包括使用模拟操作来计算反电动势的预处理部分的电动机控制装置。马达控制装置可以包括偏移补偿部分和反电动势测量部分。偏移补偿部分接收来自马达的三相电流信号，并补偿三相电流信号的偏移。反电动势测量部分接收来自电动机的补偿的电流信号和三相电压信号，并使用模拟操作来计算接收的电流信号和接收的电压信号，以提供计算结果。

3. 发明申请

US20130027094A1 TRIANGULAR WAVE GENERATOR AND METHOD GENERATING TRIANGULAR WAVE THEREOF 有权
标题翻译：三角波发生器及其三角波产生方法
公开(公告)号：US20130027094A1
公开(公告)日：2013-01-31
申请号：US13488337
申请日：2012-06-04
申请人： Hui Dong LEE , Jaewon Nam , Young Kyun Cho , Jong-Kee Kwon , Yil Suk Yang , Jongdae Kim
发明人： Hui Dong LEE , Jaewon Nam , Young Kyun Cho , Jong-Kee Kwon , Yil Suk Yang , Jongdae Kim
IPC分类号： H03K4/06
CPC分类号： H03K4/501
摘要： Disclosed is a triangular wave generator which includes a square wave signal generating unit configured to output a first signal transitioning to a high level from a low level via an output terminal in response to a first transition of a clock signal and to transition the first signal to a low level from a high level in response to a reset signal; a resistance unit configured to adjust a voltage level of a the square wave signal; and a capacitance unit configured to receive an output signal of the resistance unit to generate a second signal rising to a high level from a low level with a slope, to provide the reset signal to the square wave signal generating unit, and to output a triangular signal by falling the second signal to a low level from a high level with a slope.
摘要翻译：公开了一种三角波发生器，其包括方波信号生成单元，其被配置为响应于时钟信号的第一转换，经由输出端子输出从低电平转换到高电平的第一信号，并且将第一信号转换为响应于复位信号从高电平的低电平; 电阻单元，被配置为调整所述方波信号的电压电平; 以及电容单元，被配置为接收电阻单元的输出信号，以产生从具有斜率的低电平上升到高电平的第二信号，以将复位信号提供给方波信号生成单元，并输出三角形通过从具有斜率的高电平将第二信号降低到低电平来产生信号。

4. 发明申请

US20120268052A1 MOTOR CONTROL DEVICE AND METHOD OF CONTROLLING THE SAME 有权
标题翻译：电机控制装置及其控制方法
公开(公告)号：US20120268052A1
公开(公告)日：2012-10-25
申请号：US13443823
申请日：2012-04-10
申请人： Jaewon NAM , Young Kyun Cho , Hui Dong Lee , Yil Suk Yang , Jong-Kee Kwon , Jongdae Kim
发明人： Jaewon NAM , Young Kyun Cho , Hui Dong Lee , Yil Suk Yang , Jong-Kee Kwon , Jongdae Kim
IPC分类号： H02P23/00
CPC分类号： H02P6/182 , H02P6/085 , H02P6/10 , H02P6/18 , H02P6/21 , H02P2209/07
摘要： A motor control device including a preprocessing portion calculating a counter electromotive force using an analog operation is provided. The motor control device may include an offset compensation portion and a counter electromotive force measuring portion. The offset compensation portion receives a three-phase current signal from the motor and compensates an offset of the three-phase current signal. The counter electromotive force measuring portion receives the compensated current signal and a three-phase voltage signal from the motor and calculates the received current signal and the received voltage signal using an analog operation to provide the calculated result.
摘要翻译：提供了一种包括使用模拟操作来计算反电动势的预处理部分的电动机控制装置。马达控制装置可以包括偏移补偿部分和反电动势测量部分。偏移补偿部分接收来自马达的三相电流信号，并补偿三相电流信号的偏移。反电动势测量部分接收来自电动机的补偿的电流信号和三相电压信号，并使用模拟操作来计算接收的电流信号和接收的电压信号，以提供计算结果。

5. 发明授权

US08836259B2 Sensorless BLDC motor systems and driving methods of sensorless BLDC motor 有权
标题翻译：无传感器BLDC电机系统和无传感器BLDC电机的驱动方法
公开(公告)号：US08836259B2
公开(公告)日：2014-09-16
申请号：US13347128
申请日：2012-01-10
申请人： Young Kyun Cho , Hui Dong Lee , Jaewon Nam , Jong-Kee Kwon
发明人： Young Kyun Cho , Hui Dong Lee , Jaewon Nam , Jong-Kee Kwon
IPC分类号： H02P6/00 , H02P6/14
CPC分类号： H02P6/142 , H02P6/15
摘要： Provided is a sensorless BLDC motor system. The sensorless BLDC motor system includes a BLDC motor, a comparator, a motor controller, a three-phase inverter, and a mode selector. The BLDC motor includes first to third coils. The comparator compares a voltage of a specific coil of the first to third coils with a neutral-point voltage to output the compared result. The voltage of the specific coil becomes equal to the neutral-point voltage and a specific time elapses, and then the motor controller generates first and second coil control signals based on the compared result. The three-phase inverter supplies a source voltage or ground voltage to the specific coil, or floats the specific coil, in response to the first and second coil control signals. The mode selector selects a driving mode of the BLDC motor by adjusting the specific time.
摘要翻译：提供无传感器BLDC电机系统。无传感器BLDC电机系统包括BLDC电机，比较器，电机控制器，三相逆变器和模式选择器。 BLDC电机包括第一至第三线圈。比较器将第一至第三线圈的特定线圈的电压与中性点电压进行比较，以输出比较结果。特定线圈的电压等于中性点电压，经过一定时间，然后电机控制器根据比较结果产生第一和第二线圈控制信号。三相逆变器响应于第一和第二线圈控制信号向特定线圈提供源极电压或接地电压，或者浮动特定线圈。模式选择器通过调整具体时间来选择BLDC电机的驱动模式。

6. 发明授权

US08362938B2 Analog digital converting device 有权
标题翻译：模拟数字转换装置
公开(公告)号：US08362938B2
公开(公告)日：2013-01-29
申请号：US12982531
申请日：2010-12-30
申请人： Young Kyun Cho , Young-deuk Jeon , Jaewon Nam , Jong-Kee Kwon
发明人： Young Kyun Cho , Young-deuk Jeon , Jaewon Nam , Jong-Kee Kwon
IPC分类号： H03M1/12
CPC分类号： H03M1/145 , H03M1/365 , H03M1/468
摘要： Provided is an analog digital converting device which consumes a low power and guarantees fast operation characteristic. The analog digital converting device includes a sub-ADC and a successive approximation ADC. The sub-ADC converts an external analog signal into a first digital signal by using first and second reference voltages. The successive approximation ADC comprises a plurality of bit streams, and converts the external analog signal into a second digital signal according to a successive approximation operation using the first and second reference voltages. The successive approximation ADC receives the first digital signal, and converts the second digital signal in a state where one of the first and second reference voltages has been applied to the bit streams based on the first digital signal.
摘要翻译：提供了一种消耗低功耗并保证快速操作特性的模拟数字转换装置。模拟数字转换装置包括子ADC和逐次逼近ADC。子ADC通过使用第一和第二参考电压将外部模拟信号转换为第一数字信号。逐次逼近ADC包括多个比特流，并且根据使用第一和第二参考电压的逐次逼近操作将外部模拟信号转换为第二数字信号。逐次逼近ADC接收第一数字信号，并且在第一和第二参考电压中的一个被基于第一数字信号施加到比特流的状态下转换第二数字信号。

7. 发明申请

US20120062406A1 ANALOG DIGITAL CONVERTING DEVICE 有权
标题翻译：模拟数字转换器件
公开(公告)号：US20120062406A1
公开(公告)日：2012-03-15
申请号：US12982531
申请日：2010-12-30
申请人： Young Kyun Cho , Young-deuk Jeon , Jaewon Nam , Jong-Kee Kwon
发明人： Young Kyun Cho , Young-deuk Jeon , Jaewon Nam , Jong-Kee Kwon
IPC分类号： H03M1/36 , H03M1/12
CPC分类号： H03M1/145 , H03M1/365 , H03M1/468
摘要： Provided is an analog digital converting device which consumes a low power and guarantees fast operation characteristic. The analog digital converting device includes a sub-ADC and a successive approximation ADC. The sub-ADC converts an external analog signal into a first digital signal by using first and second reference voltages. The successive approximation ADC comprises a plurality of bit streams, and converts the external analog signal into a second digital signal according to a successive approximation operation using the first and second reference voltages. The successive approximation ADC receives the first digital signal, and converts the second digital signal in a state where one of the first and second reference voltages has been applied to the bit streams based on the first digital signal.
摘要翻译：提供了一种消耗低功耗并保证快速操作特性的模拟数字转换装置。模拟数字转换装置包括子ADC和逐次逼近ADC。子ADC通过使用第一和第二参考电压将外部模拟信号转换为第一数字信号。逐次逼近ADC包括多个比特流，并且根据使用第一和第二参考电压的逐次逼近操作将外部模拟信号转换为第二数字信号。逐次逼近ADC接收第一数字信号，并且在第一和第二参考电压中的一个被基于第一数字信号施加到比特流的状态下转换第二数字信号。

8. 发明申请

US20120146821A1 PIPELINED ANALOG DIGITAL CONVERTOR 有权
标题翻译：管道模拟数字转换器
公开(公告)号：US20120146821A1
公开(公告)日：2012-06-14
申请号：US13309872
申请日：2011-12-02
申请人： Jaewon NAM , Young-deuk Jeon , Young Kyun Cho , Jong-Kee Kwon
发明人： Jaewon NAM , Young-deuk Jeon , Young Kyun Cho , Jong-Kee Kwon
IPC分类号： H03M1/12 , H03M1/06
CPC分类号： H03M1/069 , H03M1/168
摘要： Disclosed is a pipelined analog-to-digital converter which includes a digital correction circuit configured to improve the complexity of a logic circuit for dividing a correction period and a no-correction period of a digital output. The pipelined analog-to-digital converter performs a logic correction operation via binary shifting at data error correction. Accordingly, although the resolution increases, it is possible to reduce the complexity and area of a logic circuit.
摘要翻译：公开了一种流水线模数转换器，其包括数字校正电路，其被配置为提高用于分割校正周期和数字输出的无校正周期的逻辑电路的复杂度。流水线模数转换器通过数据纠错的二进制移位执行逻辑校正操作。因此，虽然分辨率增加，但是可以降低逻辑电路的复杂性和面积。

9. 发明申请

US20120146820A1 PIPELINED ANALOG DIGITAL CONVERTOR 有权
标题翻译：管道模拟数字转换器
公开(公告)号：US20120146820A1
公开(公告)日：2012-06-14
申请号：US13243629
申请日：2011-09-23
申请人： Jaewon NAM , Young-deuk Jeon , Young Kyun Cho , Jong-Kee Kwon
发明人： Jaewon NAM , Young-deuk Jeon , Young Kyun Cho , Jong-Kee Kwon
IPC分类号： H03M1/06 , H03M1/12
CPC分类号： H03M1/069 , H03M1/168
摘要： Disclosed is a pipelined analog-to-digital converter which includes a digital correction circuit configured to measure and correct a pipelined conversion stage gain error and an offset error due to a finite voltage gain operational amplifier and capacitor mismatch. The pipelined analog-to-digital converter includes a pipelined conversion stage error measuring and correcting circuit measuring and correcting an error generated from an conversion stage, so that an error of a conversion stage is minimized and a chip realization area and power consumption are reduced.
摘要翻译：公开了一种流水线模数转换器，其包括数字校正电路，其被配置为测量和校正流水线转换级增益误差以及由于有限电压增益运算放大器和电容器失配引起的偏移误差。流水线模数转换器包括流水线转换级误差测量和校正电路，测量和校正从转换级产生的误差，使得转换级的误差最小化，并且芯片实现面积和功耗降低。

10. 发明授权

US08564469B2 Pipelined analog digital convertor 有权
标题翻译：流水线模拟数字转换器
公开(公告)号：US08564469B2
公开(公告)日：2013-10-22
申请号：US13309872
申请日：2011-12-02
申请人： Jaewon Nam , Young-deuk Jeon , Young Kyun Cho , Jong-Kee Kwon
发明人： Jaewon Nam , Young-deuk Jeon , Young Kyun Cho , Jong-Kee Kwon
IPC分类号： H03M1/38
CPC分类号： H03M1/069 , H03M1/168
摘要： A pipelined analog-to-digital converter includes a digital correction circuit configured to improve the complexity of a logic circuit for dividing a correction period and a no-correction period of a digital output. The pipelined analog-to-digital converter performs a logic correction operation via binary shifting at data error correction. Accordingly, although the resolution increases, it is possible to reduce the complexity and area of a logic circuit.
摘要翻译：流水线模数转换器包括数字校正电路，其被配置为提高用于划分校正周期和数字输出的无校正周期的逻辑电路的复杂度。流水线模数转换器通过数据纠错的二进制移位执行逻辑校正操作。因此，虽然分辨率增加，但是可以降低逻辑电路的复杂性和面积。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式