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1. 发明申请

US20100241928A1 Data Processing System Having ECC Encoding and Decoding Circuits Therein with Code Rate Selection Based on Bit Error Rate Detection 审中-公开
标题翻译：具有基于误码率检测的码率选择的ECC编码和解码电路的数据处理系统
公开(公告)号：US20100241928A1
公开(公告)日：2010-09-23
申请号：US12716793
申请日：2010-03-03
申请人： Jaehong Kim , Yong June Kim , Junjin Kong , Seung-Hwan Song
发明人： Jaehong Kim , Yong June Kim , Junjin Kong , Seung-Hwan Song
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/618 , G06F11/1012 , H03M13/13 , H03M13/353 , H03M13/3738 , H03M13/6356 , H03M13/6362
摘要： A data processing system includes an error checking and correction (ECC) encoding circuit, an integrated circuit memory and a code rate control circuit. The ECC encoding circuit is configured to selectively apply a plurality of unique ECC code rates to write data received by the data processing system during an operation to convert the write data into encoded data, in response to a code rate selection signal. The integrated circuit memory includes a plurality of storage regions therein. These storage regions are configured to receive respective portions of the encoded data from the ECC encoding circuit. The code rate control circuit is configured to generate the code rate selection signal. This code rate selection signal has a value that specifies the corresponding ECC code rate to be applied to respective portions of the write data.
摘要翻译：数据处理系统包括纠错（ECC）编码电路，集成电路存储器和码率控制电路。 ECC编码电路被配置为响应于码率选择信号，在操作期间选择性地应用多个唯一ECC码率来写入由数据处理系统接收的数据，以将写入数据转换为编码数据。集成电路存储器包括多个存储区域。这些存储区域被配置为从ECC编码电路接收编码数据的相应部分。码率控制电路被配置为产生码率选择信号。该码率选择信号具有指定应用于写入数据的各个部分的相应的ECC码率的值。

2. 发明申请

US20100115377A1 METHOD OF ESTIMATING AND CORRECTING ERRORS IN MEMORY CELLS 有权
标题翻译：估计和校正记忆细胞中的错误的方法
公开(公告)号：US20100115377A1
公开(公告)日：2010-05-06
申请号：US12607768
申请日：2009-10-28
申请人： Jaehong Kim , Yong June Kim , Seung Hwan Song
发明人： Jaehong Kim , Yong June Kim , Seung Hwan Song
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/1108 , G06F11/1072
摘要： A method, implemented by at least an error correction code (ECC) decoder and a controller, estimates and corrects errors in memory cells. The method includes identifying a first candidate group of memory cells having an error-generation possibility using a first method for error estimation; identifying a second candidate group of memory cells having an error-generation possibility using a second method for error estimation; and correcting errors in at least one cell commonly included in the first and second candidate groups.
摘要翻译：至少由纠错码（ECC）解码器和控制器实施的方法估计和校正存储器单元中的错误。该方法包括使用第一种误差估计方法来识别具有错误产生可能性的存储器单元的第一候选组; 使用用于错误估计的第二方法识别具有错误生成可能性的第二候选组存储器单元; 以及校正通常包括在第一和第二候选组中的至少一个单元中的错误。

3. 发明授权

US08751900B2 Storage device having a non-volatile memory device and copy-back method thereof 有权
标题翻译：具有非易失性存储装置的存储装置及其复制方法
公开(公告)号：US08751900B2
公开(公告)日：2014-06-10
申请号：US13106892
申请日：2011-05-13
申请人： Yong June Kim , Hong Rak Son , Seonghyeog Choi , Junjin Kong , Yongtaew Yim , Jaehong Kim , KyoungLae Cho , Wootae Chang
发明人： Yong June Kim , Hong Rak Son , Seonghyeog Choi , Junjin Kong , Yongtaew Yim , Jaehong Kim , KyoungLae Cho , Wootae Chang
IPC分类号： G11C29/00 , H03M13/00
CPC分类号： G06F11/106 , H03M13/1102 , H03M13/136 , H03M13/152 , H03M13/155 , H03M13/2909 , H03M13/618
摘要： A storage device includes a non-volatile memory device outputting read data from a source area and a memory controller configured to execute an ECC operation on a plurality of vectors in the read data and to write the error-corrected read data into target area of the non-volatile memory device. The memory controller declares that a vector corresponding to a clean area is decoding pass without using a flag bit among the plurality of vectors during the error correction operation.
摘要翻译：存储装置包括从源区域输出读取数据的非易失性存储器装置和被配置为对读取数据中的多个向量执行ECC操作并将经纠错的读取数据写入到目标区域中的存储器控制器非易失性存储器件。存储器控制器声明对应于清洁区域的矢量是在纠错操作期间不使用多个矢量中的标志位的解码通过。

4. 发明申请

US20100115225A1 Memory Device and Memory System Including the Same 审中-公开
标题翻译：内存设备和包含其的内存系统
公开(公告)号：US20100115225A1
公开(公告)日：2010-05-06
申请号：US12577842
申请日：2009-10-13
申请人： Jaehong Kim , Heeseok Eun , Yong June Kim , Seung-Hwan Song
发明人： Jaehong Kim , Heeseok Eun , Yong June Kim , Seung-Hwan Song
IPC分类号： G06F12/00
CPC分类号： G06F3/064 , G06F3/0616 , G06F3/0679 , G11C11/5621 , G11C16/349
摘要： Provided is a memory device. The memory device includes a word line and a plurality of memory cells connected to the word line. The plurality of memory cells forms a page, and the number of sectors configuring the page and the size of each of the sectors can be changed.
摘要翻译：提供了一种存储器件。存储器件包括字线和连接到字线的多个存储器单元。多个存储单元形成页面，并且可以改变构成页面的扇区数量和每个扇区的大小。

5. 发明授权

US08773922B2 Non-volatile memory device, memory card and system, and method determining read voltage by comparing referenced program data with comparative read data 失效
标题翻译：非易失性存储器件，存储卡和系统，以及通过将参考程序数据与比较读取数据进行比较来确定读取电压的方法
公开(公告)号：US08773922B2
公开(公告)日：2014-07-08
申请号：US12614545
申请日：2009-11-09
申请人： Seung-Hwan Song , Jaehong Kim , Kyoung Lae Cho , Yong June Kim , Jun Jin Kong , Jong Han Kim
发明人： Seung-Hwan Song , Jaehong Kim , Kyoung Lae Cho , Yong June Kim , Jun Jin Kong , Jong Han Kim
IPC分类号： G11C7/06
CPC分类号： G11C16/26 , G11C11/5642 , G11C29/00 , G11C2211/5634
摘要： A non-volatile semiconductor memory device and related method of determining a read voltage are disclosed. The non-volatile semiconductor memory device includes; a memory cell array including a plurality of memory cells, a read voltage determination unit configured to determine an optimal read voltage by comparing reference data obtained during a program operation with comparative data obtained during a subsequent read operation and changing a current read voltage to a new read voltage based on a result of the comparison, and a read voltage generation unit configured to generate the new read voltage in response to a read voltage control signal provided by the read voltage determination unit.
摘要翻译：公开了一种非易失性半导体存储器件及确定读取电压的相关方法。非易失性半导体存储器件包括：包括多个存储单元的存储单元阵列，读电压确定单元，被配置为通过将在编程操作期间获得的参考数据与在随后的读取操作期间获得的比较数据进行比较来确定最佳读取电压，并将当前读取电压改变为新的基于比较结果的读取电压和读取电压生成单元，被配置为响应于由读取电压确定单元提供的读取电压控制信号而产生新的读取电压。

6. 发明授权

US08316279B2 Method of estimating and correcting errors in memory cells 有权
标题翻译：估计和纠正存储单元错误的方法
公开(公告)号：US08316279B2
公开(公告)日：2012-11-20
申请号：US12607768
申请日：2009-10-28
申请人： Jaehong Kim , Yong June Kim , Seung Hwan Song
发明人： Jaehong Kim , Yong June Kim , Seung Hwan Song
IPC分类号： G11C29/00
CPC分类号： H03M13/1108 , G06F11/1072
摘要： A method, implemented by at least an error correction code (ECC) decoder and a controller, estimates and corrects errors in memory cells. The method includes identifying a first candidate group of memory cells having an error-generation possibility using a first method for error estimation; identifying a second candidate group of memory cells having an error-generation possibility using a second method for error estimation; and correcting errors in at least one cell commonly included in the first and second candidate groups.
摘要翻译：至少由纠错码（ECC）解码器和控制器实施的方法估计并校正存储器单元中的错误。该方法包括使用第一种误差估计方法来识别具有错误产生可能性的存储器单元的第一候选组; 使用用于错误估计的第二方法识别具有错误生成可能性的第二候选组存储器单元; 以及校正通常包括在第一和第二候选组中的至少一个单元中的错误。

7. 发明授权

US08510624B2 Data processing system with concatenated encoding and decoding structure 有权
标题翻译：具有连接编解码结构的数据处理系统
公开(公告)号：US08510624B2
公开(公告)日：2013-08-13
申请号：US12687666
申请日：2010-01-14
申请人： Jaehong Kim , Junjin Kong , Yong June Kim
发明人： Jaehong Kim , Junjin Kong , Yong June Kim
IPC分类号： H03M13/00 , H03M13/03 , H04Q1/20 , H04L27/00
CPC分类号： G06F11/10 , H03M13/1102 , H03M13/15 , H03M13/1515 , H03M13/152 , H03M13/23 , H03M13/2707 , H03M13/271 , H03M13/2906 , H03M13/2909 , H03M13/2927 , H03M13/2957
摘要： A data processing system includes a memory configured to receive data and an encoder configured to encode data being transferred to the memory. The encoder includes an outer encoder configured to generate an outer codeword by encoding the data being transferred to the memory, and an inner encoder configured to generate a plurality of inner codewords by encoding the outer codeword.
摘要翻译：数据处理系统包括被配置为接收数据的存储器和被配置为对传送到存储器的数据进行编码的编码器。编码器包括：外部编码器，其被配置为通过对正被传送到存储器的数据进行编码来产生外部码字;以及内部编码器，被配置为通过对外部码字进行编码来生成多个内部码字。

8. 发明申请

US20100238705A1 NONVOLATILE MEMORY DEVICE AND METHOD SYSTEM INCLUDING THE SAME 审中-公开
标题翻译：非易失性存储器件和包括其的方法系统
公开(公告)号：US20100238705A1
公开(公告)日：2010-09-23
申请号：US12698720
申请日：2010-02-02
申请人： Yong June Kim , Jaehong Kim , Junjin Kong
发明人： Yong June Kim , Jaehong Kim , Junjin Kong
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C7/1006 , G11C7/1042 , G11C8/10 , G11C11/5628 , G11C11/5678 , G11C13/00 , G11C13/0004 , G11C13/0061 , G11C13/0069 , G11C2211/5623
摘要： A nonvolatile memory device performs interleaving of data to be stored in each wordline (memory page), or of data to be stored in multiple wordlines (memory pages). The NVM includes a memory cell array, a storage circuit of a de-interleaving circuit, and a read/write circuit. The storage circuit of the de-interleaving circuit is configured to store program data to be written interleaved into the memory cell array. The read/write circuit is configured to control the interleaved/deinterleaved data input/output between the memory cell array and the storage circuit. The write operation unit size may be the same or different from the read operation unit size. The storage circuit stores the program data of integer k times of a common divisor of a read operation unit size and a write operation unit size of the read/write circuit, wherein k may equal ‘m’ (the number of bits stored in each memory cell of the NVM).
摘要翻译：非易失性存储器件执行要存储在每个字线（存储器页）中的数据或要存储在多个字线（存储器页）中的数据的交织。 NVM包括存储单元阵列，解交织电路的存储电路和读/写电路。解交织电路的存储电路被配置为将要被交织的程序数据存储到存储单元阵列中。读/写电路被配置为控制存储单元阵列和存储电路之间的交错/去交织的数据输入/输出。写入操作单元尺寸可以与读取操作单元尺寸相同或不同。存储电路存储读/写电路的读操作单元大小和写操作单元大小的公约数的整数k倍的程序数据，其中k可以等于“m”（存储在每个存储器中的位数 NVM的单元）。

9. 发明申请

US20100235711A1 Data Processing System with Concatenated Encoding and Decoding Structure 有权
标题翻译：具有连续编码和解码结构的数据处理系统
公开(公告)号：US20100235711A1
公开(公告)日：2010-09-16
申请号：US12687666
申请日：2010-01-14
申请人： Jaehong Kim , Junjin Kong , Yong June Kim
发明人： Jaehong Kim , Junjin Kong , Yong June Kim
IPC分类号： H03M13/29 , G06F11/10
CPC分类号： G06F11/10 , H03M13/1102 , H03M13/15 , H03M13/1515 , H03M13/152 , H03M13/23 , H03M13/2707 , H03M13/271 , H03M13/2906 , H03M13/2909 , H03M13/2927 , H03M13/2957
摘要： A data processing system includes a memory configured to receive data and an encoder configured to encode data being transferred to the memory. The encoder includes an outer encoder configured to generate an outer codeword by encoding the data being transferred to the memory, and an inner encoder configured to generate a plurality of inner codewords by encoding the outer codeword.
摘要翻译：数据处理系统包括被配置为接收数据的存储器和被配置为对传送到存储器的数据进行编码的编码器。编码器包括：外部编码器，其被配置为通过对正被传送到存储器的数据进行编码来产生外部码字;以及内部编码器，被配置为通过对外部码字进行编码来生成多个内部码字。

10. 发明授权

US08806302B2 Semiconductor memory device and data processing method thereof 有权
标题翻译：半导体存储器件及其数据处理方法
公开(公告)号：US08806302B2
公开(公告)日：2014-08-12
申请号：US12654578
申请日：2009-12-23
申请人： Yong June Kim , Junjin Kong , Jaehong Kim , Hong Rak Son
发明人： Yong June Kim , Junjin Kong , Jaehong Kim , Hong Rak Son
IPC分类号： G11C29/00
CPC分类号： G11C13/00 , G11C7/1006 , G11C11/5628 , G11C13/0033 , G11C16/3427 , G11C29/00
摘要： Provided is a data processing method in a semiconductor memory device. The data processing method arranges data, which is to be programmed in a row and column of a nonvolatile memory device, in a row or column direction. The data processing method encodes the programmed data into a modulation code in the row or column direction such that adjacent pairs of memory cells of the nonvolatile memory device are prevented from being programmed into first and second states.
摘要翻译：提供了一种半导体存储器件中的数据处理方法。数据处理方法按行或列方向排列要编程在非易失性存储器件的行和列中的数据。数据处理方法将编程数据编码成行或列方向的调制码，使得非易失性存储器件的相邻存储单元对被阻止被编程到第一和第二状态。

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