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1. 发明申请

US20090239369A1 Method of Forming Electrical Interconnects within Insulating Layers that Form Consecutive Sidewalls 有权
标题翻译：在形成连续侧壁的绝缘层内形成电气互连的方法
公开(公告)号：US20090239369A1
公开(公告)日：2009-09-24
申请号：US12051223
申请日：2008-03-19
申请人： Jae-hak Kim , Jing Hui Li , Wu Ping Liu , Johnny Widodo
发明人： Jae-hak Kim , Jing Hui Li , Wu Ping Liu , Johnny Widodo
IPC分类号： H01L21/31 , H01L21/44
CPC分类号： H01L21/31144 , H01L21/76802 , H01L21/76808 , H01L21/76814 , H01L2221/1063
摘要： Methods of forming integrated circuit device having electrical interconnects include forming an electrically insulating layer on a substrate and forming a hard mask on the electrically insulating layer. The hard mask and the electrically insulating layer are selectively etched in sequence using a mask to define an opening therein. This opening, which may be a via hole, exposes inner sidewalls of the hard mask and the electrically insulating layer. The inner sidewall of the hard mask is then recessed relative to the inner sidewall of the electrically insulating layer and a sacrificial reaction layer is formed on the inner sidewall of the electrically insulating layer. This reaction layer operates to recess the inner sidewall of the electrically insulating layer. The reaction layer is then removed to define a wider opening having relatively uniform sidewalls. This wider opening is then filled with an electrical interconnect.
摘要翻译：形成具有电互连的集成电路器件的方法包括在衬底上形成电绝缘层并在电绝缘层上形成硬掩模。使用掩模依次选择性地蚀刻硬掩模和电绝缘层，以在其中限定开口。该开口（其可以是通孔）暴露硬掩模和电绝缘层的内侧壁。然后硬掩模的内侧壁相对于电绝缘层的内侧壁凹陷，并且牺牲反应层形成在电绝缘层的内侧壁上。该反应层操作以使电绝缘层的内侧壁凹陷。然后去除反应层以限定具有相对均匀侧壁的较宽开口。然后用更宽的开口填充电互连。

2. 发明授权

US07687381B2 Method of forming electrical interconnects within insulating layers that form consecutive sidewalls including forming a reaction layer on the inner sidewall 有权
标题翻译：在形成连续侧壁的绝缘层内形成电互连的方法，包括在内侧壁上形成反应层
公开(公告)号：US07687381B2
公开(公告)日：2010-03-30
申请号：US12051223
申请日：2008-03-19
申请人： Jae-hak Kim , Jing Hui Li , Wu Ping Liu , Johnny Widodo
发明人： Jae-hak Kim , Jing Hui Li , Wu Ping Liu , Johnny Widodo
IPC分类号： H01L21/46 , H01L21/4763 , H01L21/302 , H01L21/461
CPC分类号： H01L21/31144 , H01L21/76802 , H01L21/76808 , H01L21/76814 , H01L2221/1063
摘要： Methods of forming integrated circuit device having electrical interconnects include forming an electrically insulating layer on a substrate and forming a hard mask on the electrically insulating layer. The hard mask and the electrically insulating layer are selectively etched in sequence using a mask to define an opening therein. This opening, which may be a via hole, exposes inner sidewalls of the hard mask and the electrically insulating layer. The inner sidewall of the hard mask is then recessed relative to the inner sidewall of the electrically insulating layer and a sacrificial reaction layer is formed on the inner sidewall of the electrically insulating layer. This reaction layer operates to recess the inner sidewall of the electrically insulating layer. The reaction layer is then removed to define a wider opening having relatively uniform sidewalls. This wider opening is then filled with an electrical interconnect.
摘要翻译：形成具有电互连的集成电路器件的方法包括在衬底上形成电绝缘层并在电绝缘层上形成硬掩模。使用掩模依次选择性地蚀刻硬掩模和电绝缘层，以在其中限定开口。该开口（其可以是通孔）暴露硬掩模和电绝缘层的内侧壁。然后硬掩模的内侧壁相对于电绝缘层的内侧壁凹陷，并且牺牲反应层形成在电绝缘层的内侧壁上。该反应层操作以使电绝缘层的内侧壁凹陷。然后去除反应层以限定具有相对均匀侧壁的较宽开口。然后用更宽的开口填充电互连。

3. 发明授权

US07737029B2 Methods of forming metal interconnect structures on semiconductor substrates using oxygen-removing plasmas and interconnect structures formed thereby 有权
标题翻译：使用除氧等离子体和由此形成的互连结构在半导体衬底上形成金属互连结构的方法
公开(公告)号：US07737029B2
公开(公告)日：2010-06-15
申请号：US12050354
申请日：2008-03-18
申请人： Jae-hak Kim , Griselda Bonilla , Steven E. Molis , Darryl D. Restaino , Hosadurga Shobha , Johnny Widodo
发明人： Jae-hak Kim , Griselda Bonilla , Steven E. Molis , Darryl D. Restaino , Hosadurga Shobha , Johnny Widodo
IPC分类号： H01L21/321
CPC分类号： H01L23/53233 , H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/76876 , H01L21/76883 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming devices include forming a first electrically insulating layer having a metal interconnection therein, on a substrate and then forming a first electrically insulating barrier layer on an upper surface of the metal interconnection and on the first electrically insulating layer. The first electrically insulating barrier layer is exposed to a plasma that penetrates the first electrically insulating barrier and removes oxygen from an upper surface of the metal interconnection. The barrier layer may have a thickness in a range from about 5 Å to about 50 Å and the plasma may be a hydrogen-containing plasma that converts oxygen on the upper surface of the metal interconnection to water.
摘要翻译：形成器件的方法包括在衬底上形成其中具有金属互连的第一电绝缘层，然后在金属互连的上表面上和第一电绝缘层上形成第一电绝缘阻挡层。第一电绝缘阻挡层暴露于穿过第一电绝缘屏障并从金属互连的上表面除去氧的等离子体。阻挡层的厚度可以在约5至约埃的范围内，等离子体可以是将金属互连的上表面上的氧转化为水的含氢等离子体。

4. 发明申请

US20090280637A1 Method of manufacturing semiconductor device including ultra low dielectric constant layer 审中-公开
标题翻译：包括超低介电常数层的半导体器件的制造方法
公开(公告)号：US20090280637A1
公开(公告)日：2009-11-12
申请号：US12453326
申请日：2009-05-07
申请人： Kyoung-woo Lee , Hong-jae Shin , Jae-hak Kim , Jae-ouk Choo
发明人： Kyoung-woo Lee , Hong-jae Shin , Jae-hak Kim , Jae-ouk Choo
IPC分类号： H01L21/768
CPC分类号： H01L21/7682 , H01L21/02126 , H01L21/02203 , H01L21/02271 , H01L21/02282 , H01L21/02304 , H01L21/02348 , H01L21/02351 , H01L21/02362 , H01L21/31695
摘要： Provided is a method of manufacturing a semiconductor device. The method employs multi-step removal on a plurality of different porogens included in a low dielectric layer both before and after metal lines are formed, thereby facilitating formation of an ultra low dielectric constant layer which is used as an insulation layer between metal lines of a semiconductor device. The method may include forming an interlayer dielectric layer on a substrate, forming a plurality of porogens in the interlayer dielectric layer, removing a portion of the plurality of porogens in the interlayer dielectric layer to form a plurality of first pores in the interlayer dielectric layer, forming a wiring pattern where the plurality of first pores are formed, and removing the remaining porogens of the plurality of porogens to form a plurality of second pores in the interlayer dielectric layer.
摘要翻译：提供一种制造半导体器件的方法。该方法在形成金属线之前和之后，在包含在低电介质层中的多个不同的致孔剂上采用多步除去，从而有助于形成超低介电常数层，该超低介电常数层用作金属线之间的绝缘层半导体器件。该方法可以包括在衬底上形成层间电介质层，在层间电介质层中形成多个致孔剂，去除层间电介质层中的多个致孔剂的一部分，以在层间电介质层中形成多个第一孔，形成其中形成有多个第一孔的布线图案，并且除去多个致孔剂中剩余的孔隙原，以在层间电介质层中形成多个第二孔。

5. 发明申请

US20060063376A1 Method of fabricating dual damascene interconnections of microelectronic device using diffusion barrier layer against base material 有权
标题翻译：使用扩散阻挡层对基材的微电子器件的双镶嵌互连的方法
公开(公告)号：US20060063376A1
公开(公告)日：2006-03-23
申请号：US11195404
申请日：2005-08-02
申请人： Kyoung-woo Lee , Jae-yeol Maeng , Jae-hak Kim , Il-whan Oh , Hong-jae Shin
发明人： Kyoung-woo Lee , Jae-yeol Maeng , Jae-hak Kim , Il-whan Oh , Hong-jae Shin
IPC分类号： H01L21/4763 , H01L21/31
CPC分类号： H01L21/76808 , H01L21/02134 , H01L21/3124 , H01L21/76826
摘要： Methods of fabricating dual damascene interconnections suitable for use in microelectronic devices and similar applications using a diffusion barrier layer to protect against base materials during processing are provided. The methods include the steps of: filling a via with a hydrogen silsesquioxane (HSQ)-based filler as expressed by the general chemical formula: (RSiO3/2)x(HSiO3/2)y, wherein x and y satisfy the relationships x+y=1 and 0
摘要翻译：提供了适用于微电子器件的双镶嵌互连的方法和使用扩散阻挡层在加工期间防止基底材料的类似应用。所述方法包括以下步骤：用以通式（RSiO 3/2/2）x（HSiO 3/2/2）表示的氢倍半硅氧烷（HSQ））填充通孔 y，其中x和y满足关系x + y = 1和0

6. 发明授权

US06828229B2 Method of manufacturing interconnection line in semiconductor device 有权
标题翻译：在半导体器件中制造互连线的方法
公开(公告)号：US06828229B2
公开(公告)日：2004-12-07
申请号：US10081661
申请日：2002-02-22
申请人： Soo-geun Lee , Hong-jae Shin , Kyoung-woo Lee , Jae-hak Kim
发明人： Soo-geun Lee , Hong-jae Shin , Kyoung-woo Lee , Jae-hak Kim
IPC分类号： H01L214763
CPC分类号： H01L21/76808 , H01L21/31111 , H01L21/31116 , H01L21/31144
摘要： A method of forming an interconnection line in a semiconductor device is provided. A first etching stopper is formed on a lower conductive layer which is formed on a semiconductor substrate. A first interlayer insulating layer is formed on the first etching stopper. A second etching stopper is formed on the first interlayer insulating layer. A second interlayer insulating layer is formed on the second etching stopper. The second interlayer insulating layer, the second etching stopper, and the first interlayer insulating layer are sequentially etched using the first etching stopper as an etching stopping point to form a via hole aligned with the lower conductive layer. A protective layer is formed to protect a portion of the first etching stopper exposed at the bottom of the via hole. A portion of the second interlayer insulating layer adjacent to the via hole is etched using the second etching stopper as an etching stopping point to form a trench connected to the via hole. The protective layer is removed. The portion of the first etching stopper positioned at the bottom of the via hole is removed. An upper conductive layer that fills the via hole and the trench and is electrically connected to the lower conductive layer is formed.
摘要翻译：提供了一种在半导体器件中形成互连线的方法。在形成在半导体衬底上的下导电层上形成第一蚀刻阻挡层。在第一蚀刻停止件上形成第一层间绝缘层。在第一层间绝缘层上形成第二蚀刻阻挡层。在第二蚀刻停止件上形成第二层间绝缘层。使用第一蚀刻停止器作为蚀刻停止点，依次蚀刻第二层间绝缘层，第二蚀刻停止层和第一层间绝缘层，以形成与下导电层对准的通孔。形成保护层以保护暴露在通孔底部的第一蚀刻终止部分。使用第二蚀刻停止器蚀刻与通孔相邻的第二层间绝缘层的一部分作为蚀刻停止点，以形成连接到通孔的沟槽。保护层被去除。位于通孔底部的第一蚀刻停止部分被去除。形成填充通孔和沟槽并与下导电层电连接的上导电层。

7. 发明申请

US20060151593A1 System and method for displaying received data using separate device 有权
标题翻译：使用单独设备显示接收到的数据的系统和方法
公开(公告)号：US20060151593A1
公开(公告)日：2006-07-13
申请号：US11324585
申请日：2006-01-04
申请人： Jae-hak Kim
发明人： Jae-hak Kim
IPC分类号： G06F17/00
CPC分类号： H04L51/14
摘要： A method and apparatus for displaying received data using a separate device that makes a user's receiving terminal, that has received only a unique code of data, transmit the unique code to a separate display device connected to the Internet, and which makes the display device access a server, in which the data is stored, and display the data corresponding to the unique code. The apparatus displays received data using a code generation unit for generating a first unique code that matches metadata received from a data server that stores the data and the metadata, a first communication unit for transmitting the first unique code to a receiving terminal, and a second communication unit for receiving a second unique code from a display device and transmitting the stored metadata that matches the first unique code to the display device if the first unique code corresponds to the second unique code.
摘要翻译：一种用于使用仅接收唯一的数据代码的用户接收终端的独立设备来显示接收的数据的方法和装置，将唯一的代码发送到连接到因特网的单独的显示设备，并且使显示设备访问存储数据的服务器，并显示对应于唯一代码的数据。该装置使用代码生成单元显示接收到的数据，该代码生成单元用于生成与从存储数据和元数据的数据服务器接收的元数据相匹配的第一唯一码，用于将第一唯一码发送到接收终端的第一通信单元，通信单元，用于从显示设备接收第二唯一代码，并且如果所述第一唯一码对应于所述第二唯一码，则将与所述第一唯一码匹配的所存储的元数据发送到所述显示设备。

8. 发明授权

US06858727B2 Intermediate of carbapenem antibiotics and process for the preparation thereof 失效
标题翻译：碳青霉烯类抗生素中间体及其制备方法
公开(公告)号：US06858727B2
公开(公告)日：2005-02-22
申请号：US10344267
申请日：2001-08-06
申请人： Cheol-hae Lee , Bong-jin Kim , Do-kyu Pyun , Won-jang Jeong , Jae-hak Kim , Hee-jung Chung , Hyun-jung Kwak , Eun-jung Kim , Shin-seup Song , Yong-ho Chung
发明人： Cheol-hae Lee , Bong-jin Kim , Do-kyu Pyun , Won-jang Jeong , Jae-hak Kim , Hee-jung Chung , Hyun-jung Kwak , Eun-jung Kim , Shin-seup Song , Yong-ho Chung
IPC分类号： C07D413/14 , C07D205/08 , C07D265/06 , C07D265/14 , C07D413/06 , C07D487/04 , C07D498/10 , C07F7/18 , C07F9/572 , C07F9/6561 , C07F9/568
CPC分类号： C07D413/06 , C07D205/08 , C07D265/06 , C07D265/14 , C07D487/04 , C07F9/65611 , Y02P20/55
摘要： There is disclosed an azetidinone compound of the formula (I): wherein R is hydrogen, or a hydroxy protecting group, R1 and R2 are each independently alkyl of 1-15 carbon atoms, benzyl or cyclized together with the carbon atom to which they are attached to form a 5 or 6-membered cyclic hydrocarbon or a heterocyclic radical having one or two hetero ring atoms, said hetero ring atoms being selected from the group consisting of O and S; R3 is lower alkyl or —COO(lower alkyl) R4 is phenyl, or phenyl substituted with halogen, lower alkoxy or nitro which is useful as a synthetic intermediate to the 1′β-methylcarbapenem-type antibacterial agent.
摘要翻译：公开了式（I）的氮杂环丁酮化合物：其中R是氢或羟基保护基，R 1和R 2各自独立地是1-15个碳原子的烷基，或与它们所在的碳原子一起环化连接以形成具有一个或两个杂环原子的5或6元环烃或杂环基团，所述杂环原子选自O和S; R3是低级烷基或-COO（低级烷基）R4是苯基，或被卤素，低级烷氧基或硝基取代的苯基，其可用作1'-二甲基碳青霉烯型抗菌剂的合成中间体。

9. 发明授权

US07690557B2 System and method for displaying received data using separate device 有权
标题翻译：使用单独设备显示接收到的数据的系统和方法
公开(公告)号：US07690557B2
公开(公告)日：2010-04-06
申请号：US11324585
申请日：2006-01-04
申请人： Jae-hak Kim
发明人： Jae-hak Kim
IPC分类号： G06F17/00
CPC分类号： H04L51/14
摘要： A method and apparatus for displaying received data using a separate device that makes a user's receiving terminal, that has received only a unique code of data, transmit the unique code to a separate display device connected to the Internet, and which makes the display device access a server, in which the data is stored, and display the data corresponding to the unique code. The apparatus displays received data using a code generation unit for generating a first unique code that matches metadata received from a data server that stores the data and the metadata, a first communication unit for transmitting the first unique code to a receiving terminal, and a second communication unit for receiving a second unique code from a display device and transmitting the stored metadata that matches the first unique code to the display device if the first unique code corresponds to the second unique code.
摘要翻译：一种用于使用仅接收唯一的数据代码的用户接收终端的独立设备来显示接收的数据的方法和装置，将唯一的代码发送到连接到因特网的单独的显示设备，并且使显示设备访问存储数据的服务器，并显示对应于唯一代码的数据。该装置使用代码生成单元显示接收到的数据，该代码生成单元用于生成与从存储数据和元数据的数据服务器接收的元数据相匹配的第一唯一码，用于将第一唯一码发送到接收终端的第一通信单元，通信单元，用于从显示设备接收第二唯一代码，并且如果所述第一唯一码对应于所述第二唯一码，则将与所述第一唯一码匹配的所存储的元数据发送到所述显示设备。

10. 发明授权

US07323407B2 Method of fabricating dual damascene interconnections of microelectronic device using diffusion barrier layer against base material 有权
标题翻译：使用扩散阻挡层对基材的微电子器件的双镶嵌互连的方法
公开(公告)号：US07323407B2
公开(公告)日：2008-01-29
申请号：US11195404
申请日：2005-08-02
申请人： Kyoung-woo Lee , Jae-yeol Maeng , Jae-hak Kim , Il-whan Oh , Hong-jae Shin
发明人： Kyoung-woo Lee , Jae-yeol Maeng , Jae-hak Kim , Il-whan Oh , Hong-jae Shin
IPC分类号： H01L21/311 , H01L23/52
CPC分类号： H01L21/76808 , H01L21/02134 , H01L21/3124 , H01L21/76826
摘要： Methods of fabricating dual damascene interconnections suitable for use in microelectronic devices and similar applications using a diffusion barrier layer to protect against base materials during processing are provided. The methods include the steps of: filling a via with a hydrogen silsesquioxane (HSQ)-based filler as expressed by the general chemical formula: (RSiO3/2)x(HSiO3/2)y, wherein x and y satisfy the relationships x+y=1 and 0
摘要翻译：提供了适用于微电子器件的双镶嵌互连的方法和使用扩散阻挡层在加工期间防止基底材料的类似应用。所述方法包括以下步骤：用以通式（RSiO 3/2/2）x（HSiO 3/2/2）表示的氢倍半硅氧烷（HSQ））填料填充通孔 y，其中x和y满足关系x + y = 1和0

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