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1. 发明授权

US06717861B2 Non-volatile semiconductor memory device capable of preventing program disturb due to noise voltage induced at a string select line and program method thereof 有权
标题翻译：能够防止由串选择线引起的噪声电压引起的程序干扰的非易失性半导体存储装置及其编程方法
公开(公告)号：US06717861B2
公开(公告)日：2004-04-06
申请号：US10006196
申请日：2001-12-04
申请人： Jae-Yong Jeong , Sung-Soo Lee
发明人： Jae-Yong Jeong , Sung-Soo Lee
IPC分类号： G11C1604
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/10 , G11C16/3418
摘要： Disclosed is a non-volatile semiconductor memory device including a circuit for controlling potentials of select lines and word lines in accordance with bit line setup, string select line setup, program and discharge periods of a program cycle. The control circuit biases a string select line to a power supply voltage during the bit line setup period in the program cycle, and to a voltage between the power supply voltage and ground voltage during the string select line setup and the program periods. According to the string select line control scheme, program disturb due to a noise voltage induced at a string select line when a program voltage is applied to a word line adjacent to the string select line is prevented.
摘要翻译：公开了一种非易失性半导体存储器件，其包括根据位线设置，串选择线设置，编程周期的编程和放电周期来控制选择线和字线的电位的电路。控制电路在编程周期中的位线建立期间将串选择线偏置为电源电压，并且在串选择线设置和程序周期期间将电源电压和接地电压之间的电压偏置。根据串选择线控制方案，防止当将编程电压施加到与串选择线相邻的字线时在串选择线处感应到的噪声电压时的程序干扰。

2. 发明授权

US06614688B2 Method of programming non-volatile semiconductor memory device 有权
公开(公告)号：US06614688B2
公开(公告)日：2003-09-02
申请号：US09990191
申请日：2001-11-20
申请人： Jae-Yong Jeong , Jin-Seon Yeom , Sung-Soo Lee
发明人： Jae-Yong Jeong , Jin-Seon Yeom , Sung-Soo Lee
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C16/0483
摘要： A method of programming a non-volatile semiconductor memory device is provided. The method includes a bitline setup step, a well bias setup step, a program step, and a discharge step. In the bitline setup step, either a ground or power supply voltage is supplied respectively to bitlines according to data bits stored in page buffers, and a pocket P-well area is biased with the ground voltage. In the well bias setup step, the ground voltage applied to the pocket P-well area is cut off to make the second well area attain a floating state. Under such a condition, the pocket P-well area is biased with a coupling voltage, which is lower than the ground voltage, through a coupling capacitance between the pocket P-well area and a common source line, or a coupling capacitance between the pocket P-well area and an N-well area. In the program step, a program voltage is supplied to selected wordlines and a pass voltage is supplied to unselected wordlines, with the floating second well area biased with the coupling voltage. Therefore, the pocket P-well area is biased with a negative voltage through the capacitance coupling.

3. 发明授权

US06891754B2 Nonvolatile semiconductor memory with a programming operation and the method thereof 有权
公开(公告)号：US06891754B2
公开(公告)日：2005-05-10
申请号：US10927716
申请日：2004-08-27
申请人： Jae-Yong Jeong , Sung-Soo Lee
发明人： Jae-Yong Jeong , Sung-Soo Lee
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/24 , G11C7/00
CPC分类号： G11C16/24 , G11C16/0483 , G11C16/10
摘要： The invention provides a method of programming in a nonvolatile semiconductor memory device, having a plurality of memory cell strings connected to a plurality of bitlines and constructed of a plurality of memory cell transistors whose gates are coupled to a plurality of wordlines, and a plurality of registers corresponding to the bitlines. The method involves applying a first voltage to a first one of the bitlines and applying a second voltage to a second one of the bitline, the first bitline being adjacent to the second bitline, the first and second voltages being supplied from the registers; electrically isolating the first and second bitlines from their corresponding registers; charging the first bitline up to a third voltage higher than the first voltage and lower than the second voltage; and applying a fourth voltage to a wordline after cutting off current paths into the first and second bitlines.

4. 发明授权

US06807098B2 Nonvolatile semiconductor memory with a programming operation and the method thereof 有权
公开(公告)号：US06807098B2
公开(公告)日：2004-10-19
申请号：US10659634
申请日：2003-09-09
申请人： Jae-Yong Jeong , Sung-Soo Lee
发明人： Jae-Yong Jeong , Sung-Soo Lee
IPC分类号： G11C1604
CPC分类号： G11C16/24 , G11C16/0483 , G11C16/10
摘要： The invention provides a method of programming in a nonvolatile semiconductor memory device, having a plurality of memory cell strings connected to a plurality of bitlines and constructed of a plurality of memory cell transistors whose gates are coupled to a plurality of wordlines, and a plurality of registers corresponding to the bitlines. The method involves applying a first voltage to a first one of the bitlines and applying a second voltage to a second one of the bitline, the first bitline being adjacent to the second bitline, the first and second voltages being supplied from the registers; electrically isolating the first and second bitlines from their corresponding registers; charging the first bitline up to a third voltage higher than the first voltage and lower than the second voltage; and applying a fourth voltage to a wordline after cutting off current paths into the first and second bitlines.

5. 发明授权

US07024598B2 Nonvolatile semiconductor memory device with a fail bit detecting scheme and method for counting the number of fail bits 有权
公开(公告)号：US07024598B2
公开(公告)日：2006-04-04
申请号：US10003390
申请日：2001-10-30
申请人： Jae-Yong Jeong , Sung-Soo Lee
发明人： Jae-Yong Jeong , Sung-Soo Lee
IPC分类号： G06F11/00 , G11C29/00
CPC分类号： G11C29/44 , G11C29/40
摘要： A nonvolatile semiconductor memory device has a special test mode and circuitry for counting its own fail bits. During the test mode, test data is stored in the memory, and also in a special expected data buffer. The test data stored in the memory cells are then compared to that stored in the expected data buffer. Where there is no correspondence, fail bits are detected. The lack of correspondence is registered, counted, and output to a data output buffer block.

6. 发明申请

US20050030790A1 Nonvolatile semiconductor memory with a programming operation and the method thereof 有权
标题翻译：具有编程操作的非易失性半导体存储器及其方法
公开(公告)号：US20050030790A1
公开(公告)日：2005-02-10
申请号：US10927716
申请日：2004-08-27
申请人： Jae-Yong Jeong , Sung-Soo Lee
发明人： Jae-Yong Jeong , Sung-Soo Lee
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/24 , G11C11/34
CPC分类号： G11C16/24 , G11C16/0483 , G11C16/10
摘要： The invention provides a method of programming in a nonvolatile semiconductor memory device, having a plurality of memory cell strings connected to a plurality of bitlines and constructed of a plurality of memory cell transistors whose gates are coupled to a plurality of wordlines, and a plurality of registers corresponding to the bitlines. The method involves applying a first voltage to a first one of the bitlines and applying a second voltage to a second one of the bitline, the first bitline being adjacent to the second bitline, the first and second voltages being supplied from the registers; electrically isolating the first and second bitlines from their corresponding registers; charging the first bitline up to a third voltage higher than the first voltage and lower than the second voltage; and applying a fourth voltage to a wordline after cutting off current paths into the first and second bitlines.
摘要翻译：本发明提供了一种在非易失性半导体存储器件中进行编程的方法，该方法具有连接到多个位线的多个存储单元串，并且由多个存储单元晶体管组成，多个存储单元晶体管的栅极耦合到多个字线，与位线对应的寄存器。所述方法包括将第一电压施加到位线中的第一位置，并将第二电压施加到所述位线中的第二位置，所述第一位线与所述第二位线相邻，所述第一和第二电压从所述寄存器提供; 将第一和第二位线与其对应的寄存器电隔离; 将第一位线充电至高于第一电压并低于第二电压的第三电压; 以及在将当前路径切断到所述第一和第二位线之后，将第四电压施加到字线。

7. 发明授权

US06650566B2 Nonvolatile semiconductor memory with a programming operation and the method thereof 有权
公开(公告)号：US06650566B2
公开(公告)日：2003-11-18
申请号：US10021639
申请日：2001-12-12
申请人： Jae-Yong Jeong , Sung-Soo Lee
发明人： Jae-Yong Jeong , Sung-Soo Lee
IPC分类号： G11C1604
CPC分类号： G11C16/24 , G11C16/0483 , G11C16/10
摘要： The invention provides a method of programming in a nonvolatile semiconductor memory device, having a plurality of memory cell strings connected to a plurality of bitlines and constructed of a plurality of memory cell transistors whose gates are coupled to a plurality of wordlines, and a plurality of registers corresponding to the bitlines. The method involves applying a first voltage to a first one of the bitlines and applying a second voltage to a second one of the bitline, the first bitline being adjacent to the second bitline, the first and second voltages being supplied from the registers; electrically isolating the first and second bitlines from their corresponding registers; charging the first bitline up to a third voltage higher than the first voltage and lower than the second voltage; and applying a fourth voltage to a wordline after cutting off current paths into the first and second bitlines.

8. 发明授权

US07787305B2 Flash memory devices and programming methods that vary programming conditions in response to a selected step increment 有权
标题翻译：闪存器件和编程方法可以响应于选定的步进增量而改变编程条件
公开(公告)号：US07787305B2
公开(公告)日：2010-08-31
申请号：US12134648
申请日：2008-06-06
申请人： In-Mo Kim , Jae-Yong Jeong , Chi-Weon Yoon
发明人： In-Mo Kim , Jae-Yong Jeong , Chi-Weon Yoon
IPC分类号： G11C16/04
CPC分类号： G11C16/10
摘要： A flash memory device includes a flash memory cell array having flash memory cells arranged with word and bit lines, a word line driver circuit configured to drive the word lines at a selected step increment during a programming operation, a bulk-voltage supply circuit configured to supply a bulk voltage into a bulk of the flash memory cell array and a writing circuit configured to drive the bit lines selected by conditions during a programming operation. A control logic block is configured to control the writing circuit and the bulk-voltage supply circuit during the programming operation. The control logic block is configured to cause the writing circuit and/or the bulk-voltage supply circuit to change at least one of the conditions of the writing circuit and/or the bulk voltage responsive to the selected step increment.
摘要翻译：一种闪速存储器件包括：闪存单元阵列，具有布置有字线和位线的闪速存储器单元;字线驱动器电路，被配置为在编程操作期间以选定的阶跃增量驱动所述字线，所述体电压电源电路被配置为将大容量电压提供到闪存单元阵列的大部分中;以及写入电路，其被配置为驱动在编程操作期间由条件选择的位线。控制逻辑块被配置为在编程操作期间控制写入电路和体电压电源电路。控制逻辑块被配置为使得写入电路和/或体电压电源电路响应于所选择的步进增量来改变写入电路和/或体电压的条件中的至少一个。

9. 发明授权

US07474566B2 Non-volatile memory device and method capable of re-verifying a verified memory cell 有权
标题翻译：能够重新验证经过验证的存储单元的非易失性存储器件和方法
公开(公告)号：US07474566B2
公开(公告)日：2009-01-06
申请号：US11763606
申请日：2007-06-15
申请人： Kee-Ho Jung , Jae-Yong Jeong , Chi-Weon Yoon
发明人： Kee-Ho Jung , Jae-Yong Jeong , Chi-Weon Yoon
IPC分类号： G11C16/06
CPC分类号： G11C16/3454
摘要： A method of driving a non-volatile memory device includes programming a plurality of memory cells based on a first data copied from a program data buffer to a verification data buffer, verifying the memory cells by overwriting a result of the verification of the programmed memory cells to a verification data buffer, and re-verifying the memory cells by repeating the programming and verifying operations at least once with respect to the memory cells that were successfully verified, based on the verification result written to the verification data buffer. A non-volatile memory device includes a program data buffer storing first data, a verification data buffer copying and storing the first data, a plurality of memory cells programmed based on the data stored in the verification data buffer, a comparator comparing data stored in the verification data buffer with data read out from the programmed memory cells and outputting comparison data generated based on a result of the comparison to the verification data buffer, and a control unit controlling the program data buffer, the verification data buffer, the memory cells, and the comparator to additionally program or verify the memory cells that were successfully verified, based on the first data.
摘要翻译：驱动非易失性存储器件的方法包括：基于从程序数据缓冲器复制到验证数据缓冲器的第一数据来编程多个存储器单元，通过覆盖编程的存储器单元的验证结果来验证存储器单元并且基于写入验证数据缓冲器的验证结果，通过重复对相对于成功验证的存储器单元的编程和验证操作至少一次来重新验证存储器单元。非易失性存储装置包括存储第一数据的程序数据缓冲器，复制和存储第一数据的验证数据缓冲器，基于存储在验证数据缓冲器中的数据编程的多个存储器单元，比较存储在验证数据缓冲器中的数据的比较器验证数据缓冲器，其具有从编程的存储器单元读出的数据，并输出基于与验证数据缓冲器的比较结果生成的比较数据;以及控制单元，控制程序数据缓冲器，验证数据缓冲器，存储器单元和所述比较器基于所述第一数据额外编程或验证已成功验证的存储器单元。

10. 发明申请

US20080137435A1 Flash memory devices that support incremental step-pulse programming using nonuniform verify time intervals 有权
标题翻译：使用非均匀验证时间间隔支持增量式步进脉冲编程的闪存设备
公开(公告)号：US20080137435A1
公开(公告)日：2008-06-12
申请号：US12031422
申请日：2008-02-14
申请人： Soo-Han Kim , Jae-Yong Jeong
发明人： Soo-Han Kim , Jae-Yong Jeong
IPC分类号： G11C16/06
CPC分类号： G11C16/12 , G11C16/3454 , G11C16/3459
摘要： Nonvolatile memory devices support programming and verify operations that improve threshold-voltage distribution within programmed memory cells. This improvement is achieved by reducing a magnitude of the programming voltage steps and increasing a duration of the verify operations once at least one of the plurality of memory cells undergoing programming has been verified as a “passed” memory cell. The nonvolatile memory device includes an array of nonvolatile memory cells and a control circuit, which is electrically coupled to the array of nonvolatile memory cells. The control circuit is configured to perform a plurality of memory programming operations (P) by driving a selected word line in the array with a first stair step sequence of program voltages having first step height (e.g., ΔV1) and then, in response to verifying that at least one of the memory cells coupled to the selected word line is a passed memory cell, driving the selected word line with a second stair step sequence of program voltages having a second step height (e.g., ΔV2) lower than the first step height.
摘要翻译：非易失性存储器件支持编程和验证操作，以改善程序存储单元内的阈值电压分布。一旦将经历编程的多个存储器单元中的至少一个已经被验证为“传递”的存储器单元，则通过减小编程电压步长的大小并增加验证操作的持续时间来实现这种改进。非易失性存储器件包括非易失性存储器单元的阵列和电耦合到非易失性存储单元阵列的控制电路。控制电路被配置为通过以具有第一台阶高度（例如，DeltaV 1）的编程电压的第一阶梯顺序驱动阵列中的选定字线来执行多个存储器编程操作（P），然后响应于验证耦合到所选择的字线的存储器单元中的至少一个是经过的存储单元，用具有低于第一个字线的第二阶梯高度（例如，DeltaV 2）的编程电压的第二阶梯顺序驱动所选择的字线步高。

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