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1. 发明授权

US5920504A Semiconductor memory having embedding lockable cells 失效
标题翻译：半导体存储器具有嵌入式可锁定单元
公开(公告)号：US5920504A
公开(公告)日：1999-07-06
申请号：US928488
申请日：1997-09-12
申请人： Seung-Keun Lee , Jin-Seon Yeom
发明人： Seung-Keun Lee , Jin-Seon Yeom
IPC分类号： G11C16/02 , G11C14/00 , G11C16/04 , G11C16/22
CPC分类号： G11C16/22
摘要： A semiconductor memory is disclosed having lockable cells which can be programmed or erased to store the information of an erasure lock or an erasure unlock without disturbing data stored in memory cells. The memory includes a memory cell array formed of a plurality of blocks, the blocks formed of a plurality of memory cells which are coupled to a plurality of memory word lines and bit lines, a lockable cell array formed of a plurality of lockable cells which are coupled to a lockable bit line and a plurality of lockable word lines which are electrically isolated from the memory word lines, and a lockable decoding circuit to generate a plurality of decoding signals to select the lockable word lines independent upon a selection of the memory word lines.
摘要翻译：公开了一种半导体存储器，其具有可编程或擦除的可锁定单元，以存储擦除锁定信息或擦除解锁，而不会干扰存储在存储单元中的数据。所述存储器包括由多个块形成的存储单元阵列，所述存储单元阵列由耦合到多个存储器字线和位线的多个存储器单元形成，由多个可锁定单元形成的可锁定单元阵列，耦合到可锁定位线和与存储器字线电隔离的多个可锁定字线;以及可锁定解码电路，用于产生多个解码信号，以独立于存储器字线的选择来选择可锁定字线。

2. 发明授权

US06366487B1 Plurality of integrated circuit chips 有权
标题翻译：多种集成电路芯片
公开(公告)号：US06366487B1
公开(公告)日：2002-04-02
申请号：US09474880
申请日：1999-12-29
申请人： Jin-Seon Yeom
发明人： Jin-Seon Yeom
IPC分类号： G11C702
CPC分类号： G11C16/20 , G11C8/12 , G11C16/08
摘要： A package according to the invention comprises at least two integrated circuit (IC) chips encapsulated therein. Each of the IC chips has its option pad, and the option pads of the IC chips are biased, at the package level, to different logic levels so as to distinguish between the IC chips. Particularly, the chips of the present invention have identical address coding scheme and are each comprised of a memory cell array for storing data; a command register for activating one of master signals each indicative of a read mode, a program mode and an erase mode in response to an externally applied command; and a chip disable circuit coupled to a corresponding option pad, for determining whether or not a corresponding semiconductor memory device is selected, and for resetting the command register so as to disable the activated master signal when the corresponding semiconductor memory device is unselected.
摘要翻译：根据本发明的封装包括封装在其中的至少两个集成电路（IC）芯片。每个IC芯片都有其选件焊盘，并且IC芯片的选件焊盘在封装级别被偏置到不同的逻辑电平，以区分IC芯片。特别地，本发明的芯片具有相同的地址编码方案，并且各自包括用于存储数据的存储单元阵列; 命令寄存器，用于响应于外部施加的命令来激活每个表示读取模式，编程模式和擦除模式的主信号之一; 以及芯片禁止电路，其耦合到相应的选件焊盘，用于确定是否选择了相应的半导体存储器件，并且用于复位所述命令寄存器，以便在对应的半导体存储器件未被选择时禁用所激活的主信号。

3. 发明授权

US06614688B2 Method of programming non-volatile semiconductor memory device 有权
公开(公告)号：US06614688B2
公开(公告)日：2003-09-02
申请号：US09990191
申请日：2001-11-20
申请人： Jae-Yong Jeong , Jin-Seon Yeom , Sung-Soo Lee
发明人： Jae-Yong Jeong , Jin-Seon Yeom , Sung-Soo Lee
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C16/0483
摘要： A method of programming a non-volatile semiconductor memory device is provided. The method includes a bitline setup step, a well bias setup step, a program step, and a discharge step. In the bitline setup step, either a ground or power supply voltage is supplied respectively to bitlines according to data bits stored in page buffers, and a pocket P-well area is biased with the ground voltage. In the well bias setup step, the ground voltage applied to the pocket P-well area is cut off to make the second well area attain a floating state. Under such a condition, the pocket P-well area is biased with a coupling voltage, which is lower than the ground voltage, through a coupling capacitance between the pocket P-well area and a common source line, or a coupling capacitance between the pocket P-well area and an N-well area. In the program step, a program voltage is supplied to selected wordlines and a pass voltage is supplied to unselected wordlines, with the floating second well area biased with the coupling voltage. Therefore, the pocket P-well area is biased with a negative voltage through the capacitance coupling.

4. 发明授权

US5936890A Semiconductor flash memory having page buffer for verifying programmed memory cells 失效
标题翻译：具有页面缓冲器的半导体闪速存储器用于验证编程的存储器单元
公开(公告)号：US5936890A
公开(公告)日：1999-08-10
申请号：US122555
申请日：1998-07-24
申请人： Jin Seon Yeom
发明人： Jin Seon Yeom
IPC分类号： G11C16/02 , G11C16/06 , G11C16/10 , G11C16/34
CPC分类号： G11C16/3459 , G11C16/10 , G11C16/3454
摘要： A semiconductor memory includes a plurality of memory cells being electrically programmed and coupled to word lines and bit lines. A first latch circuit holds data during a programming operation including a verifying step. A second latch circuit generates a result from verifying a programmed memory cell, in response to the data held in the first latch circuit.
摘要翻译：半导体存储器包括电子编程并耦合到字线和位线的多个存储单元。第一锁存电路在包括验证步骤的编程操作期间保持数据。响应于保持在第一锁存电路中的数据，第二锁存电路产生验证编程存储器单元的结果。

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