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1. 发明授权

US06965528B2 Memory device having high bus efficiency of network, operating method of the same, and memory system including the same 有权
标题翻译：具有网络总线效率高的存储器件，其操作方法和包括其的存储器系统
公开(公告)号：US06965528B2
公开(公告)日：2005-11-15
申请号：US10641637
申请日：2003-08-14
申请人： Jae-Hyeong Lee , Jung-Bae Lee , Dong-Yang Lee
发明人： Jae-Hyeong Lee , Jung-Bae Lee , Dong-Yang Lee
IPC分类号： G11C7/00 , G06F13/16 , G11C7/10 , G11C7/22 , G11C11/4076
CPC分类号： G11C11/4076 , G06F13/1647 , G11C7/1045 , G11C7/22 , G11C2207/2281 , G11C2207/229
摘要： A memory device having a high bus efficiency on a network, an operating method of the memory device, and a memory system including the memory device are provided. The memory device includes banks, a programming register, and a controller. Each of the banks has a plurality of memory cells arranged in a matrix of rows and columns. In a write operation, the programming register stores simultaneous write information on how many banks there are in which data are stored. In a read operation, the controller selects one of the banks subjected to the write operation in response to the simultaneous write information to read out the memory cell data in the selected bank.
摘要翻译：提供了一种在网络上具有高总线效率的存储器件，存储器件的操作方法以及包括存储器件的存储器系统。存储器件包括存储体，编程寄存器和控制器。每个存储体具有以行和列的矩阵排列的多个存储单元。在写入操作中，编程寄存器存储关于存储了哪些数据的存储器的同时写入信息。在读取操作中，控制器响应于同时写入信息来选择经过写入操作的存储体之一，以读出所选择的存储体中的存储器单元数据。

2. 发明授权

US07173871B2 Semiconductor memory device and method of outputting data strobe signal thereof 失效
标题翻译：半导体存储器件及其数据选通信号的输出方法
公开(公告)号：US07173871B2
公开(公告)日：2007-02-06
申请号：US10392582
申请日：2003-03-19
申请人： Eun-Youp Kong , Jun-Young Jeon , Jae-Hyeong Lee
发明人： Eun-Youp Kong , Jun-Young Jeon , Jae-Hyeong Lee
IPC分类号： G11C17/18 , G11C8/00
CPC分类号： G11C7/1063 , G11C7/1051 , G11C7/1066
摘要： A semiconductor memory device is disclosed. The device comprises at least one data input/output reference signal input and output pin and a plurality of integrated circuits, each with a data input/output reference signal input and output pad connected to the data input/output reference signal input and output pin. Each integrated circuit further comprises a data input/output reference signal input and output buffer for buffering a data input/output reference signal input from the data input/output reference signal input and output pad when data is input. This buffer also buffers an internally generated data input/output reference signal, and outputs the buffered signal when data is output. The internally generated data input/output reference signal output can be disabled on each integrated circuit in response to a control signal, thus allowing a single one of the plurality of integrated circuits to be selected to generate the reference signal.
摘要翻译：公开了一种半导体存储器件。该装置包括至少一个数据输入/输出参考信号输入和输出引脚和多个集成电路，每个集成电路具有连接到数据输入/输出参考信号输入和输出引脚的数据输入/输出参考信号输入和输出焊盘。每个集成电路还包括数据输入/输出参考信号输入和输出缓冲器，用于在输入数据时缓冲从数据输入/输出参考信号输入和输出焊盘输入的数据输入/输出参考信号。该缓冲器还缓冲内部生成的数据输入/输出参考信号，并在输出数据时输出缓冲信号。可以响应于控制信号在每个集成电路上禁用内部产生的数据输入/输出参考信号输出，从而允许选择多个集成电路中的单个集成电路以产生参考信号。

3. 发明授权

US5715206A Dynamic random access memory having sequential word line refresh 失效
标题翻译：具有顺序字线刷新的动态随机存取存储器
公开(公告)号：US5715206A
公开(公告)日：1998-02-03
申请号：US701672
申请日：1996-08-22
申请人： Jae-Hyeong Lee , Hyung-Kyu Lim
发明人： Jae-Hyeong Lee , Hyung-Kyu Lim
IPC分类号： G11C11/34 , G11C11/406 , G11C11/407 , G11C7/00 , G11C8/00
CPC分类号： G11C11/406
摘要： A DRAM includes a refresh controller including a clock control section for producing a refresh mode signal in response to an external control clock signal, a refresh logic section for producing an enable signal in response to the refresh mode signal, a refresh counter for sequentially producing a first plurality of row address signals during an active period of a row address strobe signal in response to the enable signal, a row address buffer for producing a second plurality of row address signals in response to the row address signals, and a row decoder including a plurality of word line drivers which sequentially decode the second plurality of row address signals provided from the row address buffer and sequentially enables word lines corresponding to the decoded row address signals.
摘要翻译： DRAM包括刷新控制器，该刷新控制器包括响应于外部控制时钟信号产生刷新模式信号的时钟控制部分，用于响应于刷新模式信号产生使能信号的刷新逻辑部分，用于依次产生一个刷新计数器响应于使能信号在行地址选通信号的有效周期期间的第一多个行地址信号，用于响应于行地址信号产生第二多个行地址信号的行地址缓冲器，以及包括多个字线驱动器，其顺序地解码从行地址缓冲器提供的第二多行行地址信号，并且顺序地启用与解码的行地址信号相对应的字线。

4. 发明授权

US5687128A Power supply voltage boosting circuit of semiconductor memory device 失效
标题翻译：半导体存储器件的电源升压电路
公开(公告)号：US5687128A
公开(公告)日：1997-11-11
申请号：US551005
申请日：1995-10-31
申请人： Jae-Hyeong Lee , Yong-Sik Seok
发明人： Jae-Hyeong Lee , Yong-Sik Seok
IPC分类号： G11C11/407 , G11C5/14 , G11C11/4074 , G11C13/00
CPC分类号： G11C5/145 , G11C11/4074
摘要： An active power supply voltage boosting circuit for a semiconductor memory device according to the present invention causes operation of the active cycle boosted voltage generating circuit to elevate the level of the boosted power supply voltage V.sub.PP when the detected level of the boosted power supply voltage V.sub.PP is lower than a target voltage level. Thus, the boosted power supply voltage V.sub.PP can be stably maintained to the target voltage level. When the boosted power supply voltage V.sub.PP becomes higher than the target voltage level, generation of the boosted power supply voltage V.sub.PP is stopped, and as a result, unwanted consumption of the electrical current and also the damage to the semiconductor memory device by high voltage can be prevented.
摘要翻译：根据本发明的用于半导体存储器件的有源电源电压升压电路使检测到的升压电源电压VPP的电平为VPP时，主动周期升压电压产生电路的操作提升升压电源电压VPP的电平低于目标电压电平。因此，可以将升压电源电压VPP稳定地维持在目标电压电平。当升压电源电压VPP变得高于目标电压电平时，升压的电源电压VPP的产生被停止，结果，电流的不必要的消耗以及高电压对半导体存储器件的损坏被阻止

5. 发明授权

US06901018B2 Method of generating initializing signal in semiconductor memory device 有权
标题翻译：在半导体存储器件中产生初始化信号的方法
公开(公告)号：US06901018B2
公开(公告)日：2005-05-31
申请号：US10632572
申请日：2003-08-01
申请人： Il-Man Bae , Jae-Hoon Kim , Jae-Hyeong Lee
发明人： Il-Man Bae , Jae-Hoon Kim , Jae-Hyeong Lee
IPC分类号： G11C7/20 , G11C11/4072 , G11C7/00
CPC分类号： G11C7/20 , G11C11/4072
摘要： A method for generating an initializing signal capable of preventing inner circuits installed in a semiconductor memory device from being initially unstably operated due to the application of external electric power. The method includes the steps of: (a) receiving a precharge command for precharging the semiconductor memory device; (b) activating the initializing signal to a first level in response to the received precharge command; (c) receiving a refresh command for refreshing the semiconductor memory device after receipt of the precharge command; (d) receiving a mode set command for setting an operational mode of the semiconductor memory device after receipt of the refresh command; and (e) deactivating the initializing signal to a second level in response to the received mode set command. An alternative method includes the step of (a) receiving a mode set command foe initializing an inner circuit in a semiconductor memory device and (b) generating a control signal in response to the received mode set command and using the control signal as the initializing signal.
摘要翻译：一种用于产生初始化信号的方法，其能够防止安装在半导体存储器件中的内部电路由于外部电力的施加而最初不稳定地操作。该方法包括以下步骤：（a）接收用于对半导体存储器件预充电的预充电命令; （b）响应于接收到的预充电命令，将初始化信号激活到第一电平; （c）在接收到预充电命令之后接收用于刷新半导体存储器件的刷新命令; （d）在接收到刷新命令之后接收用于设置半导体存储器件的操作模式的模式设置命令; 以及（e）响应于接收的模式设置命令，将初始化信号去激活到第二电平。一种替代方法包括以下步骤：（a）接收模式设置命令对象，初始化半导体存储器件中的内部电路，（b）响应于所接收的模式设置命令产生控制信号，并使用控制信号作为初始化信号。

6. 发明授权

US5467032A Word line driver circuit for a semiconductor memory device 失效
标题翻译：用于半导体存储器件的字线驱动电路
公开(公告)号：US5467032A
公开(公告)日：1995-11-14
申请号：US332794
申请日：1994-11-02
申请人： Jae-Hyeong Lee
发明人： Jae-Hyeong Lee
IPC分类号： G11C11/407 , G11C8/08 , H03K19/017 , G11C8/00
CPC分类号： G11C8/08
摘要： A word line driver circuit for use in a semiconductor memory device for driving a word line of the memory device to a word line driving voltage having a voltage level greater than that of a power supply voltage includes a control circuit and a word line driving circuit. The word line driving circuit includes a pull-up transistor which is connected in series between the word line driving voltage and the word line, a transfer transistor connected in series between a row decoding signal and the gate electrode of the pull-up transistor. The control circuit generates a transfer output signal which is applied to the gate electrode of the transfer transistor. In a first operating mode, the transfer output signal has a voltage level greater than the power supply voltage by an amount equal to the threshold voltage of the transfer transistor, and, in a second operating mode, the transfer output signal has a voltage level equal to the power supply voltage. In the first operating mode, the gate of the pull-up transistor is precharged to the power supply voltage, prior to the execution of a memory read/write operation. In the second operating mode, the word line is driven to the voltage level of the word line driving signal, via the channel of the pull-up transistor.
摘要翻译：一种用于半导体存储器件的字线驱动电路，用于将存储器件的字线驱动到电压电平大于电源电压的字线驱动电压，包括控制电路和字线驱动电路。字线驱动电路包括串联连接在字线驱动电压和字线之间的上拉晶体管，串联连接在行解码信号和上拉晶体管的栅电极之间的转移晶体管。控制电路产生施加到转移晶体管的栅电极的转移输出信号。在第一操作模式中，传输输出信号的电压电平大于电源电压等于传输晶体管的阈值电压的量，并且在第二操作模式中，传送输出信号具有相等的电压电平到电源电压。在第一操作模式中，在执行存储器读/写操作之前，将上拉晶体管的栅极预充电到电源电压。在第二操作模式中，字线经由上拉晶体管的沟道被驱动到字线驱动信号的电压电平。

7. 发明授权

US6058495A Multi-bit test circuit in semiconductor memory device and method thereof 失效
标题翻译：半导体存储器件中的多位测试电路及其方法
公开(公告)号：US6058495A
公开(公告)日：2000-05-02
申请号：US854300
申请日：1997-05-12
申请人： Hi-Choon Lee , Jae-Hyeong Lee
发明人： Hi-Choon Lee , Jae-Hyeong Lee
IPC分类号： G01R31/28 , G11C11/401 , G11C29/00 , G11C29/28 , G11C29/34 , G11C29/44 , G11C7/00
CPC分类号： G11C29/44 , G11C29/28
摘要： A multi-bit test circuit detects the fail cells in a memory block accurately even though there exists a short bridge between bit lines or between memory cells. The circuit includes an input buffer for transferring a same test data bit received from a multi-bit input/output pin to selected ones of the memory cells in each block in response to a multi-bit test enable signal, a plurality of sense amplifier drivers connected to the respective memory cells, for amplifying the test data bits to transfer the amplified data bits to the associated memory cells, and reading out the test data bits stored into the associated memory cells, and a comparator for comparing the same data bits stored into the same block to generate a comparison data bit in response to the multi-bit input/output enable signal, and transferring the comparison data to the multi-bit input/output pin.
摘要翻译：即使在位线之间或存储器单元之间存在短桥，多位测试电路也能精确地检测存储器块中的故障单元。电路包括输入缓冲器，用于响应于多位测试使能信号，将从多位输入/输出引脚接收的相同测试数据位传送到每个块中的选择的存储单元;多个读出放大器驱动器连接到相应的存储器单元，用于放大测试数据位以将放大的数据位传送到相关联的存储器单元，以及读出存储在相关联的存储单元中的测试数据位，以及比较器，用于将存储到相同的块，以响应于多位输入/输出使能信号产生比较数据位，并将比较数据传送到多位输入/输出引脚。

8. 发明授权

US5590079A Wafer burn-in test circuit of a semiconductor memory device 失效
标题翻译：半导体存储器件的晶片老化测试电路
公开(公告)号：US5590079A
公开(公告)日：1996-12-31
申请号：US474158
申请日：1995-06-07
申请人： Jae-Hyeong Lee , Yong-sik Seok
发明人： Jae-Hyeong Lee , Yong-sik Seok
IPC分类号： G11C11/413 , G01R31/28 , G11C11/401 , G11C11/407 , G11C29/00 , G11C29/06 , G11C29/50 , G11C7/00
CPC分类号： G11C29/50 , G01R31/2856 , G11C11/401
摘要： A wafer burn-in test circuit for sensing a defective cell of a semiconductor memory device having a plurality of memory cells connected to a word line and a row decoder for selecting the word line. The burn-in test includes a word line driver circuit having an input coupled to a row decoding signal generated by the row decoder, and an ouput coupled to the word line, a control circuit having a first input coupled to a burn-in voltage signal, and a second input coupled to a control signal, and an electrical line connected between the word line driver circuit and the control circuit. In a normal mode of operation, the word line driver circuit is responsive to the row decoding signal for raising the word line to an enable voltage level. In a burn-in test mode of operation, the control circuit is responsive to the control signal for applying a burn-in voltage to the word line via the electrical line and the word line driver circuit.
摘要翻译：一种用于感测具有连接到字线的多个存储单元的半导体存储器件的缺陷单元的晶片老化测试电路以及用于选择字线的行解码器。老化测试包括字线驱动器电路，其具有耦合到由行解码器产生的行解码信号的输入和耦合到字线的输出，控制电路具有耦合到老化电压信号的第一输入以及耦合到控制信号的第二输入，以及连接在字线驱动电路和控制电路之间的电线。在正常操作模式下，字线驱动电路响应行解码信号，将字线升高到使能电压电平。在老化测试操作模式中，控制电路响应于经由电线和字线驱动器电路向字线施加老化电压的控制信号。

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