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    • 3. 发明申请
    • THIN FILM TRANSISTOR ARRAY PANEL
    • 薄膜晶体管阵列
    • US20100270555A1
    • 2010-10-28
    • US12828669
    • 2010-07-01
    • Jang-Il KIMKweon-Sam HONGDoo-Hwan YOUIn-Ho PARKHyun-Duck SON
    • Jang-Il KIMKweon-Sam HONGDoo-Hwan YOUIn-Ho PARKHyun-Duck SON
    • H01L27/088H01L29/786
    • G02F1/13624G02F1/136286
    • A thin film transistor array panel includes: first and second gate lines disposed on a substrate and separated from each other; a data line intersecting the first and second gate lines; first and second thin film transistors connected to the first gate line and the data line; a third thin film transistor connected to the second gate line and having a drain electrode; and a pixel electrode including a first subpixel electrode and a second subpixel electrode, wherein the first subpixel electrode is connected to the first and third thin film transistor, the second subpixel electrode is connected to the second thin film transistor and includes a projection overlapping the drain electrode, and the projection has a first pair of edge portions that meet a first edge of the drain electrode and are substantially parallel to each other.
    • 薄膜晶体管阵列面板包括:设置在基板上并彼此分离的第一和第二栅极线; 与第一和第二栅极线相交的数据线; 连接到第一栅极线和数据线的第一和第二薄膜晶体管; 连接到第二栅极线并具有漏电极的第三薄膜晶体管; 以及包括第一子像素电极和第二子像素电极的像素电极,其中所述第一子像素电极连接到所述第一和第三薄膜晶体管,所述第二子像素电极连接到所述第二薄膜晶体管,并且包括与所述漏极 电极,并且突起具有与漏电极的第一边缘相遇并且彼此基本平行的第一对边缘部分。
    • 4. 发明申请
    • THIN FILM TRANSISTOR ARRAY PANEL
    • 薄膜晶体管阵列
    • US20080174712A1
    • 2008-07-24
    • US12018885
    • 2008-01-24
    • Jang-Il KIMKweon-Sam HONGDoo-Hwan YOUIn-Ho PAKRHyun-Duck SON
    • Jang-Il KIMKweon-Sam HONGDoo-Hwan YOUIn-Ho PAKRHyun-Duck SON
    • G02F1/1368
    • G02F1/13624G02F1/136286
    • A thin film transistor array panel includes: first and second gate lines disposed on a substrate and separated from each other; a data line intersecting the first and second gate lines; first and second thin film transistors connected to the first gate line and the data line; a third thin film transistor connected to the second gate line and having a drain electrode; and a pixel electrode including a first subpixel electrode and a second subpixel electrode, wherein the first subpixel electrode is connected to the first and third thin film transistor, the second subpixel electrode is connected to the second thin film transistor and includes a projection overlapping the drain electrode, and the projection has a first pair of edge portions that meet a first edge of the drain electrode and are substantially parallel to each other.
    • 薄膜晶体管阵列面板包括:设置在基板上并彼此分离的第一和第二栅极线; 与第一和第二栅极线相交的数据线; 连接到第一栅极线和数据线的第一和第二薄膜晶体管; 连接到第二栅极线并具有漏电极的第三薄膜晶体管; 以及包括第一子像素电极和第二子像素电极的像素电极,其中所述第一子像素电极连接到所述第一和第三薄膜晶体管,所述第二子像素电极连接到所述第二薄膜晶体管,并且包括与所述漏极 电极,并且突起具有与漏电极的第一边缘相遇并且彼此基本平行的第一对边缘部分。