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1. 发明申请

US20050184354A1 Structure for and method of fabricating a high-speed CMOS-compatible Ge-on-insulator photodetector 有权
标题翻译：制造高速CMOS兼容的绝缘体上的光电探测器的结构和方法
公开(公告)号：US20050184354A1
公开(公告)日：2005-08-25
申请号：US10785894
申请日：2004-02-24
申请人： Jack Chu , Gabriel Dehlinger , Alfred Grill , Steven Koester , Qiging Ouyang , Jeremy Schaub
发明人： Jack Chu , Gabriel Dehlinger , Alfred Grill , Steven Koester , Qiging Ouyang , Jeremy Schaub
IPC分类号： H01L31/101 , H01L31/075
CPC分类号： H01L31/101
摘要： The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n- and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by utilizing a buried insulating layer to isolate carriers generated in the underlying substrate, high quantum efficiency over a broad spectrum by utilizing a Ge absorbing layer, low voltage operation by utilizing thin a absorbing layer and narrow electrode spacings, and compatibility with CMOS devices by virtue of its planar structure and use of a group IV absorbing material. The method for fabricating the photodetector uses direct growth of Ge on thin SOI or an epitaxial oxide, and subsequent thermal annealing to achieve a high-quality absorbing layer. This method limits the amount of Si available for interdiffusion, thereby allowing the Ge layer to be annealed without causing substantial dilution of the Ge layer by the underlying Si.
摘要翻译：本发明解决了与Si CMOS技术兼容的高速高效光电探测器的问题。该结构由薄的SOI衬底上的Ge吸收层组成，并且使用隔离区，交替的n型和p型接触以及低电阻表面电极。该器件通过利用掩埋绝缘层来隔离衬底中产生的载流子，通过利用Ge吸收层在宽谱上具有高量子效率，通过利用薄的吸收层和窄电极间隔的低电压操作以及兼容性来实现高带宽通过其平面结构和使用IV族吸收材料的CMOS器件。用于制造光电检测器的方法使用在薄SOI或外延氧化物上的Ge的直接生长，以及随后的热退火以实现高质量的吸收层。该方法限制可用于相互扩散的Si的量，从而允许Ge层退火，而不会导致Ge层被下面的Si大量稀释。

2. 发明授权

US07138697B2 Structure for and method of fabricating a high-speed CMOS-compatible Ge-on-insulator photodetector 有权
公开(公告)号：US07138697B2
公开(公告)日：2006-11-21
申请号：US10785894
申请日：2004-02-24
申请人： Jack O. Chu , Gabriel K. Dehlinger , Alfred Grill , Steven J. Koester , Qiging Ouyang , Jeremy D. Schaub
发明人： Jack O. Chu , Gabriel K. Dehlinger , Alfred Grill , Steven J. Koester , Qiging Ouyang , Jeremy D. Schaub
IPC分类号： H01L31/105
CPC分类号： H01L31/101
摘要： The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n- and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by utilizing a buried insulating layer to isolate carriers generated in the underlying substrate, high quantum efficiency over a broad spectrum by utilizing a Ge absorbing layer, low voltage operation by utilizing thin a absorbing layer and narrow electrode spacings, and compatibility with CMOS devices by virtue of its planar structure and use of a group IV absorbing material. The method for fabricating the photodetector uses direct growth of Ge on thin SOI or an epitaxial oxide, and subsequent thermal annealing to achieve a high-quality absorbing layer. This method limits the amount of Si available for interdiffusion, thereby allowing the Ge layer to be annealed without causing substantial dilution of the Ge layer by the underlying Si.

3. 发明申请

US20080042215A1 STRAINED COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) ON ROTATED WAFERS AND METHODS THEREOF 失效
标题翻译：旋转补偿金属氧化物半导体（CMOS）及其方法
公开(公告)号：US20080042215A1
公开(公告)日：2008-02-21
申请号：US11925088
申请日：2007-10-26
申请人： Meikei Ieong , Qiging Ouyang , Kern Rim
发明人： Meikei Ieong , Qiging Ouyang , Kern Rim
IPC分类号： H01L29/94
CPC分类号： H01L21/823807 , H01L27/0922 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： The present invention provides CMOS structures including at least one strained pFET that is located on a rotated semiconductor substrate to improve the device performance. Specifically, the present invention utilizes a Si-containing semiconductor substrate having a (100) crystal orientation in which the substrate is rotated by about 45° such that the CMOS device channels are located along the direction. Strain can be induced upon the CMOS structure including at least a pFET and optionally an nFET, particularly the channels, by forming a stressed liner about the FET, by forming embedded stressed wells in the substrate, or by utilizing a combination of embedded stressed wells and a stressed liner. The present invention also provides methods for fabricating the aforesaid semiconductor structures.
摘要翻译：本发明提供CMOS结构，其包括位于旋转的半导体衬底上的至少一个应变pFET，以改善器件性能。具体地，本发明利用具有（100）晶体取向的含Si半导体衬底，其中衬底旋转约45°，使得CMOS器件沟道沿<100>方向定位。通过在衬底中形成嵌入的应力阱，或者通过利用嵌入的应力阱的组合，或者通过利用嵌入的应力阱的组合，可以在包括至少pFET和任选的nFET，特别是沟道的CMOS结构上诱导应变，一个紧张的班轮。本发明还提供了制造上述半导体结构的方法。

4. 发明申请

US20080261371A1 VERTICAL BIPOLAR TRANSISTOR WITH A MAJORITY CARRIER ACCUMULATION LAYER AS A SUBCOLLECTOR FOR SOI BiCMOS WITH REDUCED BURIED OXIDE THICKNESS FOR LOW-SUBSTRATE BIAS OPERATION 有权
标题翻译：具有主要载体累积层的垂直双极晶体管，作为用于SOI BiCMOS的半导体器件，具有减少的基底氧化物厚度用于低基板偏压运行
公开(公告)号：US20080261371A1
公开(公告)日：2008-10-23
申请号：US12144998
申请日：2008-06-24
申请人： Herbert L. Ho , Mahender Kumar , Qiging Ouyang , Paul A. Papworth , Christopher D. Sheraw , Michael D. Steigerwalt
发明人： Herbert L. Ho , Mahender Kumar , Qiging Ouyang , Paul A. Papworth , Christopher D. Sheraw , Michael D. Steigerwalt
IPC分类号： H01L21/331
CPC分类号： H01L29/7317 , H01L21/84 , H01L27/1203 , H01L29/0821 , H01L29/66265
摘要： The present invention provides a “subcollector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped subcollector. Instead, the inventive vertical SOI BJT uses a back gate-induced, majority carrier accumulation layer as the subcollector when it operates. The SOI substrate is biased such that the accumulation layer is formed at the bottom of the first semiconductor layer. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS. A back-gated CMOS device is also provided.
摘要翻译：本发明提供了一种不含杂质掺杂子集电极的“不带集电极的绝缘体上硅”（SOI）双极结型晶体管（BJT）。相反，本发明的垂直SOI BJT在操作时使用背栅极多数载流子积累层作为子集电极。 SOI衬底被偏置，使得积累层形成在第一半导体层的底部。这种器件的优点是其类似CMOS的工艺。因此，可以简化集成方案，并且可以显着降低制造成本。本发明还提供了使用具有厚BOX的常规SOI起始晶片在非常薄的BOX的选定区域上制造BJT的方法。双极器件下面的BOX厚度减小，可以显着降低与CMOS相容的衬底偏置，同时保持CMOS下方的厚BOX的优点。还提供了背栅CMOS装置。

5. 发明授权

US07691716B2 Vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness for low-substrate bias operation 有权
标题翻译：具有绝大多数载流子积累层的垂直双极晶体管作为用于SOI BiCMOS的子集电极，具有降低的掩埋氧化物厚度以用于低衬底偏置操作
公开(公告)号：US07691716B2
公开(公告)日：2010-04-06
申请号：US12144998
申请日：2008-06-24
申请人： Herbert L. Ho , Mahender Kumar , Qiging Ouyang , Paul A. Papworth , Christopher D. Sheraw , Michael D. Steigerwalt
发明人： Herbert L. Ho , Mahender Kumar , Qiging Ouyang , Paul A. Papworth , Christopher D. Sheraw , Michael D. Steigerwalt
IPC分类号： H01L21/331 , H01L21/8222
CPC分类号： H01L29/7317 , H01L21/84 , H01L27/1203 , H01L29/0821 , H01L29/66265
摘要： The present invention provides a “subcollector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped subcollector. Instead, the inventive vertical SOI BJT uses a back gate-induced, majority carrier accumulation layer as the subcollector when it operates. The SOI substrate is biased such that the accumulation layer is formed at the bottom of the first semiconductor layer. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS. A back-gated CMOS device is also provided.
摘要翻译：本发明提供了一种不含杂质掺杂子集电极的“不带集电极的绝缘体上硅”（SOI）双极结型晶体管（BJT）。相反，本发明的垂直SOI BJT在操作时使用背栅极多数载流子积累层作为子集电极。 SOI衬底被偏置，使得积累层形成在第一半导体层的底部。这种器件的优点是其类似CMOS的工艺。因此，可以简化集成方案，并且可以显着降低制造成本。本发明还提供了使用具有厚BOX的常规SOI起始晶片在非常薄的BOX的选定区域上制造BJT的方法。双极器件下面的BOX厚度减小，可以显着降低与CMOS相容的衬底偏置，同时保持CMOS下方的厚BOX的优点。还提供了背栅CMOS装置。

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