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1. 发明申请

US20110191055A1 METHOD AND APPARATUS FOR SELECTING VOLTAGE AND FREQUENCY LEVELS FOR USE IN AT-SPEED TESTING 失效
标题翻译：用于选择在速度测试中使用的电压和频率水平的方法和装置
公开(公告)号：US20110191055A1
公开(公告)日：2011-08-04
申请号：US12696902
申请日：2010-01-29
申请人： JOSE MARTINEZ , Chandramouli Visweswariah , Francis Woytowich , Jinjun Xiong
发明人： JOSE MARTINEZ , Chandramouli Visweswariah , Francis Woytowich , Jinjun Xiong
IPC分类号： G06F19/00 , G01R31/00 , G06F17/18
CPC分类号： G01R31/00 , G06F17/18 , G06F19/00
摘要： In one embodiment, the invention is a method and apparatus for selecting voltage and frequency levels for use in at-speed testing. One embodiment of a method for selecting a set of test conditions with which to test an integrated circuit chip includes formulating a statistical optimization problem and obtaining a solution to the statistical optimization problem, where the solution is the set of test conditions.
摘要翻译：在一个实施例中，本发明是用于选择在速度测试中使用的电压和频率水平的方法和装置。用于选择用于测试集成电路芯片的一组测试条件的方法的一个实施例包括制定统计优化问题并获得统计优化问题的解决方案，其中解是测试条件集合。

2. 发明授权

US08676536B2 Method and apparatus for selecting voltage and frequency levels for use in at-speed testing 失效
标题翻译：用于选择用于速度测试的电压和频率电平的方法和装置
公开(公告)号：US08676536B2
公开(公告)日：2014-03-18
申请号：US12696902
申请日：2010-01-29
申请人： Jose M Martinez , Chandramouli Visweswariah , Francis Woytowich , Jinjun Xiong
发明人： Jose M Martinez , Chandramouli Visweswariah , Francis Woytowich , Jinjun Xiong
IPC分类号： G06F17/18 , G01R31/00
CPC分类号： G01R31/00 , G06F17/18 , G06F19/00
摘要： In one embodiment, the invention is a method and apparatus for selecting voltage and frequency levels for use in at-speed testing. One embodiment of a method for selecting a set of test conditions with which to test an integrated circuit chip includes formulating a statistical optimization problem and obtaining a solution to the statistical optimization problem, where the solution is the set of test conditions.
摘要翻译：在一个实施例中，本发明是用于选择在速度测试中使用的电压和频率水平的方法和装置。用于选择用于测试集成电路芯片的一组测试条件的方法的一个实施例包括制定统计优化问题并获得统计优化问题的解决方案，其中解是测试条件集合。

3. 发明授权

US08359565B2 Method and apparatus for generating test patterns for use in at-speed testing 有权
标题翻译：用于生成用于速度测试的测试模式的方法和装置
公开(公告)号：US08359565B2
公开(公告)日：2013-01-22
申请号：US13439188
申请日：2012-04-04
申请人： Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
发明人： Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
IPC分类号： G06F17/50 , G06F11/22
CPC分类号： G01R31/318328 , G01R31/318342
摘要： In one embodiment, the invention is a method and apparatus generating test patterns for use in at-speed testing. One embodiment of a method for use by a general purpose computing device that is configured to generate a set of test patterns with which to test an integrated circuit chip includes receiving, by an input device of the general purpose computing device, statistical timing information relating to the integrated circuit chip and a logic circuit of the integrated circuit chip and generating, by a processor of the general purpose computing device, the set of test patterns in accordance with the statistical timing information while simultaneously selecting a set of paths on which to test the set of test patterns.
摘要翻译：在一个实施例中，本发明是产生用于在速测试中的测试图案的方法和装置。由通用计算设备使用的方法的一个实施例被配置为生成用于测试集成电路芯片的一组测试图案，包括由通用计算设备的输入设备接收与所述集成电路芯片和所述集成电路芯片的逻辑电路，并且由所述通用计算设备的处理器根据所述统计定时信息生成所述一组测试图案，同时选择一组在其上测试所述的路径一套测试模式。

4. 发明授权

US08340939B2 Method and apparatus for selecting paths for use in at-speed testing 有权
标题翻译：用于选择在速度测试中使用的路径的方法和装置
公开(公告)号：US08340939B2
公开(公告)日：2012-12-25
申请号：US12610090
申请日：2009-10-30
申请人： Yiyu Shi , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
发明人： Yiyu Shi , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
IPC分类号： G01R31/00
CPC分类号： G01R31/31835
摘要： In one embodiment, the invention is a method and apparatus for selecting paths for use in at-speed testing. One embodiment of a method for selecting a set of n paths with which to test an integrated circuit chip includes: organizing the set of n paths into a plurality of sub-sets, receiving a new candidate path, and adding the new candidate path to one of the sub-sets when the new candidate path improves the process coverage metric of the sub-sets.
摘要翻译：在一个实施例中，本发明是用于选择在速度测试中使用的路径的方法和装置。用于选择用于测试集成电路芯片的n个路径的集合的方法的一个实施例包括：将n个路径的集合组织成多个子集，接收新的候选路径，并将新的候选路径添加到一个当新的候选路径改进子集的过程覆盖度量时，子集的子集。

5. 发明授权

US08104005B2 Method and apparatus for efficient incremental statistical timing analysis and optimization 有权
标题翻译：用于高效增量统计时序分析和优化的方法和装置
公开(公告)号：US08104005B2
公开(公告)日：2012-01-24
申请号：US12244512
申请日：2008-10-02
申请人： Debjit Sinha , Natesan Venkateswaran , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
发明人： Debjit Sinha , Natesan Venkateswaran , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/10 , G06F2217/84
摘要： In one embodiment, the invention is a method and apparatus for efficient incremental statistical timing analysis and optimization. One embodiment of a method for determining an incremental extrema of n random variables, given a change to at least one of the n random variables, includes obtaining the n random variables, obtaining a first extrema for the n random variables, where the first extrema is an extrema computed prior to the change to the at least one of the n random variables, removing the at least one of the n random variables to form an (n−1) subset, computing a second extrema for the (n−1) subset in accordance with the first extrema and the at least one of the n random variables, and outputting a new extrema of the n random variables incrementally based on the extrema of the (n−1) subset and the at least one of the n random variables that changed.
摘要翻译：在一个实施例中，本发明是一种用于有效增量统计时序分析和优化的方法和装置。给定对n个随机变量中的至少一个的改变的用于确定n个随机变量的增量极值的方法的一个实施例包括获得n个随机变量，获得n个随机变量的第一极值，其中第一极值是在对所述n个随机变量中的至少一个随机变量进行改变之前计算的极值，去除所述n个随机变量中的所述至少一个以形成（n-1）子集，计算所述（n-1）子集的第二极值根据第一极值和n个随机变量中的至少一个，并且基于第（n-1）个子集的极值和n个随机变量中的至少一个来递增地输出n个随机变量的新的极值改变了。

6. 发明授权

US07886247B2 Method and apparatus for statistical path selection for at-speed testing 有权
标题翻译：用于速度测试的统计路径选择的方法和装置
公开(公告)号：US07886247B2
公开(公告)日：2011-02-08
申请号：US12111634
申请日：2008-04-29
申请人： Hanif Fatemi , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
发明人： Hanif Fatemi , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G01R31/318371
摘要： In one embodiment, the invention is a method and apparatus for statistical path selection for at-speed testing. One embodiment of a method for selecting a path of an integrated circuit chip for at-speed testing includes computing a process coverage metric for a plurality of paths in the integrated circuit chip and selecting at least one path that maximizes the process coverage metric.
摘要翻译：在一个实施例中，本发明是用于速度测试的统计路径选择的方法和装置。用于选择用于高速测试的集成电路芯片的路径的方法的一个实施例包括计算集成电路芯片中的多个路径的处理覆盖度量度，并且选择使过程覆盖度量最大化的至少一个路径。

7. 发明申请

US20080270953A1 IC CHIP AT-FUNCTIONAL-SPEED TESTING WITH PROCESS COVERAGE EVALUATION 有权
标题翻译： IC芯片功能快速测试与过程覆盖评估
公开(公告)号：US20080270953A1
公开(公告)日：2008-10-30
申请号：US11741164
申请日：2007-04-27
申请人： Eric A. Foreman , Gary D. Grise , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
发明人： Eric A. Foreman , Gary D. Grise , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/10
摘要： Methods, systems and program products for evaluating an IC chip are disclosed. In one embodiment, the method includes running a statistical static timing analysis (SSTA) of a full IC chip design; creating at-functional-speed test (AFST) robust paths for an IC chip, the created robust paths representing a non-comprehensive list of AFST robust paths for the IC chip; and re-running the SSTA with the SSTA delay model setup based on the created robust paths. A process coverage is calculated for evaluation from the SSTA runnings; and a particular IC chip is evaluated based on the process coverage.
摘要翻译：公开了用于评估IC芯片的方法，系统和程序产品。在一个实施例中，该方法包括运行全IC芯片设计的统计静态时序分析（SSTA）; 创建用于IC芯片的功能速度测试（AFST）鲁棒路径，所创建的鲁棒路径表示IC芯片的AFST鲁棒路径的非全面列表; 并基于创建的鲁棒路径，使用SSTA延迟模型设置重新运行SSTA。计算过程覆盖率用于从SSTA运行中进行评估; 并且基于处理覆盖来评估特定的IC芯片。

8. 发明申请

US20080250370A1 REPRESENTING AND PROPAGATING A VARIATIONAL VOLTAGE WAVEFORM IN STATISTICAL STATIC TIMING ANALYSIS OF DIGITAL CIRCUITS 有权
标题翻译：在数字电路的统计静态时序分析中代表和传播变量电压波形
公开(公告)号：US20080250370A1
公开(公告)日：2008-10-09
申请号：US11733058
申请日：2007-04-09
申请人： Soroush Abbaspour , David J. Hathaway , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
发明人： Soroush Abbaspour , David J. Hathaway , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： An approach that represents and propagates a variational voltage waveform in statistical static timing analysis of digital circuits is described. In one embodiment, there is a statistical static timing analysis tool for analyzing digital circuit designs. The statistical static timing analysis tool includes a variational waveform modeling component that is configured to generate a variational waveform model that approximate arbitrary waveform transformations of waveforms at nodes of a digital circuit. The variational waveform model transforms a nominal waveform into a perturbed waveform in accordance with a plurality of waveform transformation operators that account for variations that occur between the nominal waveform and the perturbed waveform. A variational waveform propagating component is configured to propagate variational waveforms through a timing arc from at least one input to at least one output of the digital circuit in accordance with the variational waveform model.
摘要翻译：描述了在数字电路的统计静态时序分析中表示和传播变化电压波形的方法。在一个实施例中，存在用于分析数字电路设计的统计静态时序分析工具。统计静态时序分析工具包括变分波形建模组件，其被配置为生成近似波形在数字电路节点处的任意波形变换的变分波形模型。变分波形模型根据考虑在标称波形和扰动波形之间出现的变化的多个波形变换算子将标称波形变换为扰动波形。变分波形传播分量被配置为根据变化波形模型将变化波形传播通过定时弧从数字电路的至少一个输入到至少一个输出。

9. 发明授权

US08510696B2 Ordering of statistical correlated quantities 失效
标题翻译：统计相关数量的排序
公开(公告)号：US08510696B2
公开(公告)日：2013-08-13
申请号：US13422637
申请日：2012-03-16
申请人： Chandramouli Visweswariah , Jinjun Xiong , Vladimir P. Zolotov
发明人： Chandramouli Visweswariah , Jinjun Xiong , Vladimir P. Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/50
摘要： Solutions for ordering of statistical correlated quantities are disclosed. In one aspect, a method includes timing a plurality of paths in an integrated circuit to determine a set of timing quantities associated with each of the plurality of paths; determining a most critical timing quantity in the set of timing quantities; forming a tiered timing quantity arrangement for ordering a plurality of timing quantities in the set of timing quantities; removing the most critical timing quantity from the set of timing quantities and placing the most critical timing quantity in an uppermost available tier of the tiered timing quantity arrangement; and repeating the determining, forming and removing for the set of timing quantities excluding the removed most critical timing quantity.
摘要翻译：公布统计相关数量排序的解决方案。在一个方面，一种方法包括对集成电路中的多个路径进行定时以确定与多个路径中的每一条相关联的一组定时量; 确定所述一组定时数量中最关键的定时数量; 形成用于在所述一组定时量中排序多个定时量的分层定时量排列; 从所述定时量集合中去除最关键的定时数量，并将最关键的定时数量置于分层定时数量排列的最上层可用层; 并且重复确定，形成和去除不包括去除的最关键定时量的一组定时量。

10. 发明授权

US08176462B2 Method and apparatus for generating test patterns for use in at-speed testing 有权
标题翻译：用于生成用于速度测试的测试模式的方法和装置
公开(公告)号：US08176462B2
公开(公告)日：2012-05-08
申请号：US12464025
申请日：2009-05-11
申请人： Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
发明人： Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
IPC分类号： G06F11/22 , G06F17/50
CPC分类号： G01R31/318328 , G01R31/318342
摘要： In one embodiment, the invention is a method and apparatus generating test patterns for use in at-speed testing. One embodiment of a method for use by a general purpose computing device that is configured to generate a set of test patterns with which to test an integrated circuit chip includes receiving, by an input device of the general purpose computing device, statistical timing information relating to the integrated circuit chip and a logic circuit of the integrated circuit chip and generating, by a processor of the general purpose computing device, the set of test patterns in accordance with the statistical timing information while simultaneously selecting a set of paths on which to test the set of test patterns.
摘要翻译：在一个实施例中，本发明是产生用于在速测试中的测试图案的方法和装置。由通用计算设备使用的方法的一个实施例被配置为生成用于测试集成电路芯片的一组测试图案，包括由通用计算设备的输入设备接收与所述集成电路芯片和所述集成电路芯片的逻辑电路，并且由所述通用计算设备的处理器根据所述统计定时信息生成所述一组测试图案，同时选择一组在其上测试的路径一套测试模式。

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