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1. 发明授权

US08104005B2 Method and apparatus for efficient incremental statistical timing analysis and optimization 有权
标题翻译：用于高效增量统计时序分析和优化的方法和装置
公开(公告)号：US08104005B2
公开(公告)日：2012-01-24
申请号：US12244512
申请日：2008-10-02
申请人： Debjit Sinha , Natesan Venkateswaran , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
发明人： Debjit Sinha , Natesan Venkateswaran , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/10 , G06F2217/84
摘要： In one embodiment, the invention is a method and apparatus for efficient incremental statistical timing analysis and optimization. One embodiment of a method for determining an incremental extrema of n random variables, given a change to at least one of the n random variables, includes obtaining the n random variables, obtaining a first extrema for the n random variables, where the first extrema is an extrema computed prior to the change to the at least one of the n random variables, removing the at least one of the n random variables to form an (n−1) subset, computing a second extrema for the (n−1) subset in accordance with the first extrema and the at least one of the n random variables, and outputting a new extrema of the n random variables incrementally based on the extrema of the (n−1) subset and the at least one of the n random variables that changed.
摘要翻译：在一个实施例中，本发明是一种用于有效增量统计时序分析和优化的方法和装置。给定对n个随机变量中的至少一个的改变的用于确定n个随机变量的增量极值的方法的一个实施例包括获得n个随机变量，获得n个随机变量的第一极值，其中第一极值是在对所述n个随机变量中的至少一个随机变量进行改变之前计算的极值，去除所述n个随机变量中的所述至少一个以形成（n-1）子集，计算所述（n-1）子集的第二极值根据第一极值和n个随机变量中的至少一个，并且基于第（n-1）个子集的极值和n个随机变量中的至少一个来递增地输出n个随机变量的新的极值改变了。

2. 发明申请

US20100088658A1 METHOD AND APPARATUS FOR EFFICIENT INCREMENTAL STATISTICAL TIMING ANALYSIS AND OPTIMIZATION 有权
标题翻译：有效增量统计时序分析与优化的方法与装置
公开(公告)号：US20100088658A1
公开(公告)日：2010-04-08
申请号：US12244512
申请日：2008-10-02
申请人： Debjit Sinha , Natesan Venkateswaran , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
发明人： Debjit Sinha , Natesan Venkateswaran , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/10 , G06F2217/84
摘要： In one embodiment, the invention is a method and apparatus for efficient incremental statistical timing analysis and optimization. One embodiment of a method for determining an incremental extrema of n random variables, given a change to at least one of the n random variables, includes obtaining the n random variables, obtaining a first extrema for the n random variables, where the first extrema is an extrema computed prior to the change to the at least one of the n random variables, removing the at least one of the n random variables to form an (n−1) subset, computing a second extrema for the (n−1) subset in accordance with the first extrema and the at least one of the n random variables, and outputting a new extrema of the n random variables incrementally based on the extrema of the (n−1) subset and the at least one of the n random variables that changed.
摘要翻译：在一个实施例中，本发明是一种用于有效增量统计时序分析和优化的方法和装置。给定对n个随机变量中的至少一个的改变的用于确定n个随机变量的增量极值的方法的一个实施例包括获得n个随机变量，获得n个随机变量的第一极值，其中第一极值是在对所述n个随机变量中的至少一个随机变量进行改变之前计算的极值，去除所述n个随机变量中的所述至少一个以形成（n-1）子集，计算所述（n-1）子集的第二极值根据第一极值和n个随机变量中的至少一个，并且基于第（n-1）个子集的极值和n个随机变量中的至少一个来递增地输出n个随机变量的新的极值改变了。

3. 发明授权

US08418107B2 Performing statistical timing analysis with non-separable statistical and deterministic variations 失效
标题翻译：用不可分的统计和确定性变化进行统计时序分析
公开(公告)号：US08418107B2
公开(公告)日：2013-04-09
申请号：US12943541
申请日：2010-11-10
申请人： Jeffrey G Hemmett , Debjit Sinha , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
发明人： Jeffrey G Hemmett , Debjit Sinha , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/504 , G06F2217/10 , G06F2217/84
摘要： In one embodiment, the invention is a method and apparatus for performing statistical timing analysis with non-separable statistical and deterministic variations. One embodiment of a method for performing timing analysis of an integrated circuit chip includes computing delays and slews of chip gates and wires, wherein the delays and slews depend on at least a first process parameter that is deterministic and corner-based and a second process parameter that is statistical and non-separable with the first process parameter, and performing a single timing run using the timing quantity, wherein the single timing run produces arrival times, required arrival times, and timing slacks at outputs, latches, and circuit nodes of the integrated circuit chip. The computed arrival times, required arrival times, and timing slacks can be projected to a corner value of deterministic variations in order to obtain a statistical model of the delays and stews at the corresponding corner.
摘要翻译：在一个实施例中，本发明是用于以不可分的统计和确定性变化执行统计时序分析的方法和装置。用于执行集成电路芯片的定时分析的方法的一个实施例包括计算芯片栅极和导线的延迟和压摆，其中所述延迟和压摆取决于至少一个确定性和基于角的第一工艺参数，以及第二工艺参数其与第一过程参数是统计的且不可分离的，并且使用定时数量执行单个定时运行，其中单个定时运行产生到达时间，所需的到达时间和定时偏移在输出，锁存器和电路节点集成电路芯片。计算的到达时间，所需的到达时间和时间休息可以被计算为确定性变化的角落值，以便获得相应角落处的延迟和炖菜的统计模型。

4. 发明授权

US08560989B2 Statistical clock cycle computation 有权
标题翻译：统计时钟周期计算
公开(公告)号：US08560989B2
公开(公告)日：2013-10-15
申请号：US13311832
申请日：2011-12-06
申请人： Nathan Buck , Brian Dreibelbis , John P. Dubuque , Eric A. Foreman , James C. Gregerson , Peter A. Habitz , Jeffrey G. Hemmett , Debjit Sinha , Natesan Venkateswaran , Chandramouli Visweswariah , Michael H. Wood , Vladimir Zolotov
发明人： Nathan Buck , Brian Dreibelbis , John P. Dubuque , Eric A. Foreman , James C. Gregerson , Peter A. Habitz , Jeffrey G. Hemmett , Debjit Sinha , Natesan Venkateswaran , Chandramouli Visweswariah , Michael H. Wood , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/10 , G06F2217/62
摘要： Systems and methods for statistical clock cycle computation and closing timing of an integrated circuit design to a maximum clock cycle or period. The method includes loading a design and timing model for at least one circuit path of an integrated circuit or a region of the integrated circuit into a computing device. The method further includes performing a statistical static timing analysis (SSTA) of the at least one circuit path using the loaded design and timing model to obtain slack canonical data. The method further includes calculating a maximum circuit clock cycle for the integrated circuit or the specified region of the integrated circuit in linear canonical form based upon the slack canonical data obtained from the SSTA.
摘要翻译：将集成电路设计的统计时钟周期计算和闭合时序的系统和方法设计到最大时钟周期或周期。该方法包括将用于集成电路或集成电路的区域的至少一个电路路径的设计和定时模型加载到计算设备中。该方法还包括使用加载的设计和定时模型来执行至少一个电路路径的统计静态时序分析（SSTA），以获得松散的规范数据。该方法还包括基于从SSTA获得的松弛规范数据，以线性规范形式计算集成电路或集成电路的指定区域的最大电路时钟周期。

5. 发明申请

US20100180243A1 Method of Performing Timing Analysis on Integrated Circuit Chips with Consideration of Process Variations 有权
标题翻译：对考虑过程变化的集成电路芯片执行时序分析的方法
公开(公告)号：US20100180243A1
公开(公告)日：2010-07-15
申请号：US12354306
申请日：2009-01-15
申请人： Debjit Sinha , Eric A. Foreman , Peter A. Habitz , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
发明人： Debjit Sinha , Eric A. Foreman , Peter A. Habitz , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method for verifying whether a circuit meets timing constraints by performing an incremental static timing analysis in which slack is represented by a distribution that includes sensitivities to various process variables. The slack at an endpoint is computed by propagating the arrival times and required arrival times of paths leading up to the endpoint. The computation of arrival and required arrival times needs the computation of delays of individual gate and wire segments in each path that leads to the endpoint. The mixed mode adds a deterministic timing to the statistical timing (DSTA+SSTA).
摘要翻译：一种用于通过执行增量静态时序分析来验证电路是否满足时序约束的方法，其中松弛由包括对各种过程变量的灵敏度的分布表示。通过传播到达端点的路径的到达时间和所需到达时间来计算端点的松弛度。到达和到达时间的计算需要计算通向端点的每个路径中各个门和线段的延迟。混合模式为统计时间（DSTA + SSTA）增加了一个确定性时序。

6. 发明授权

US08141025B2 Method of performing timing analysis on integrated circuit chips with consideration of process variations 有权
标题翻译：考虑过程变化对集成电路芯片进行时序分析的方法
公开(公告)号：US08141025B2
公开(公告)日：2012-03-20
申请号：US12354306
申请日：2009-01-15
申请人： Debjit Sinha , Eric A. Foreman , Peter A. Habitz , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
发明人： Debjit Sinha , Eric A. Foreman , Peter A. Habitz , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5031
摘要： A method for verifying whether a circuit meets timing constraints by performing an incremental static timing analysis in which slack is represented by a distribution that includes sensitivities to various process variables. The slack at an endpoint is computed by propagating the arrival times and required arrival times of paths leading up to the endpoint. The computation of arrival and required arrival times needs the computation of delays of individual gate and wire segments in each path that leads to the endpoint. The mixed mode adds a deterministic timing to the statistical timing (DSTA+SSTA).
摘要翻译：一种用于通过执行增量静态时序分析来验证电路是否满足时序约束的方法，其中松弛由包括对各种过程变量的灵敏度的分布表示。通过传播到达端点的路径的到达时间和所需到达时间来计算端点的松弛度。到达和到达时间的计算需要计算通向端点的每个路径中各个门和线段的延迟。混合模式为统计时间（DSTA + SSTA）增加了一个确定性时序。

7. 发明申请

US20130036395A1 EFFICIENT SLACK PROJECTION FOR TRUNCATED DISTRIBUTIONS 失效
标题翻译：截断分布的有效插值投影
公开(公告)号：US20130036395A1
公开(公告)日：2013-02-07
申请号：US13197320
申请日：2011-08-03
申请人： Eric A. Foreman , James C. Gregerson , Peter A. Habitz , Jeffrey G. Hemmett , Debjit Sinha , Natesan Venkateswaran , Chandramouli Visweswariah , Xiaoyue Wang , Vladmimir Zolotov
发明人： Eric A. Foreman , James C. Gregerson , Peter A. Habitz , Jeffrey G. Hemmett , Debjit Sinha , Natesan Venkateswaran , Chandramouli Visweswariah , Xiaoyue Wang , Vladmimir Zolotov
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5031
摘要： Aspects of the present invention provide solutions for projecting slack in an integrated circuit. A statistical static timing analysis (SSTA) is computed to get a set of Gaussian distributions over a plurality of variation sources in the integrated circuit. Based on the Gaussian distributions, a truncated subset and a remainder subset of the Gaussian distributions are identified. Then data factors that represent a ratio between the remainder subset and the truncated subset are obtained. These data factors are applied to the SSTA to root sum square (RSS) project the slack for the integrated circuit that takes into account the absence of the truncated subset.
摘要翻译：本发明的方面提供了用于在集成电路中突出松弛的解决方案。计算统计静态时序分析（SSTA）以在集成电路中的多个变化源上获得一组高斯分布。基于高斯分布，识别高斯分布的截断子集和余数子集。然后获得表示余数子集和截断子集之间的比率的数据因子。这些数据因子被应用于SSTA到根平方（RSS）项目，考虑到缺少截断子集的集成电路的松弛。

8. 发明申请

US20100211922A1 Method of Performing Statistical Timing Abstraction for Hierarchical Timing Analysis of VLSI circuits 有权
标题翻译：执行VLSI电路分层时序分析的统计时序抽象方法
公开(公告)号：US20100211922A1
公开(公告)日：2010-08-19
申请号：US12388932
申请日：2009-02-19
申请人： Debjit Sinha , Adil Bhanji , Barry L. Dorfman , Kerim Kalafala , Natesan Venkateswaran , Chandramouli Visweswariah
发明人： Debjit Sinha , Adil Bhanji , Barry L. Dorfman , Kerim Kalafala , Natesan Venkateswaran , Chandramouli Visweswariah
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method for performing a hierarchical statistical timing analysis of an integrated circuit (IC) chip design by abstracting one or more macros of the design. The method includes performing a statistical static timing analysis of at least one macro; performing a statistical abstraction of the macro to obtain a statistical abstract model of the macro timing characteristics; applying the statistical abstract model as the timing model for each occurrence of the macro leading to a simplified IC chip design; and performing a hierarchical statistical timing analysis of the simplified chip design. The method achieves a context aware statistical abstraction, where a generated statistical abstract model is instantiated for each macro of the chip during statistical static timing analysis at the chip level, providing a compressed and pruned statistical timing abstraction and reducing the model-size during the statistical abstraction.
摘要翻译：一种用于通过抽象设计的一个或多个宏来执行集成电路（IC）芯片设计的分层统计时序分析的方法。该方法包括执行至少一个宏的统计静态时序分析; 执行宏的统计抽象以获得宏定时特征的统计抽象模型; 将统计抽象模型应用于宏观出现的时序模型，从而实现简化的IC芯片设计; 并执行简化芯片设计的分层统计时序分析。该方法实现上下文感知统计抽象，其中在芯片级的统计静态时序分析期间为芯片的每个宏实例化生成的统计抽象模型，提供压缩和修剪的统计时序抽象并且在统计期间减小模型大小抽象。

9. 发明授权

US08458632B2 Efficient slack projection for truncated distributions 失效
标题翻译：用于截断分布的有效松弛投影
公开(公告)号：US08458632B2
公开(公告)日：2013-06-04
申请号：US13197320
申请日：2011-08-03
申请人： Eric A. Foreman , James C. Gregerson , Peter A. Habitz , Jeffrey G. Hemmett , Debjit Sinha , Natesan Venkateswaran , Chandramouli Visweswariah , Xiaoyue Wang , Vladimer Zolotov
发明人： Eric A. Foreman , James C. Gregerson , Peter A. Habitz , Jeffrey G. Hemmett , Debjit Sinha , Natesan Venkateswaran , Chandramouli Visweswariah , Xiaoyue Wang , Vladimer Zolotov
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5031
摘要： Aspects of the present invention provide solutions for projecting slack in an integrated circuit. A statistical static timing analysis (SSTA) is computed to get a set of Gaussian distributions over a plurality of variation sources in the integrated circuit. Based on the Gaussian distributions, a truncated subset and a remainder subset of the Gaussian distributions are identified. Then data factors that represent a ratio between the remainder subset and the truncated subset are obtained. These data factors are applied to the SSTA to root sum square (RSS) project the slack for the integrated circuit that takes into account the absence of the truncated subset.
摘要翻译：本发明的方面提供了用于在集成电路中突出松弛的解决方案。计算统计静态时序分析（SSTA）以在集成电路中的多个变化源上获得一组高斯分布。基于高斯分布，识别高斯分布的截断子集和余数子集。然后获得表示余数子集和截断子集之间的比率的数据因子。这些数据因子被应用于SSTA到根平方（RSS）项目，考虑到缺少截断子集的集成电路的松弛。

10. 发明授权

US08122404B2 Performing a statistical timing abstraction for a hierarchical timing analysis of VLSI circuits 有权
标题翻译：对VLSI电路的分层定时分析执行统计时序抽象
公开(公告)号：US08122404B2
公开(公告)日：2012-02-21
申请号：US12388932
申请日：2009-02-19
申请人： Debjit Sinha , Adil Bhanji , Barry L. Dorfman , Kerim Kalafala , Natesan Venkateswaran , Chandramouli Visweswariah
发明人： Debjit Sinha , Adil Bhanji , Barry L. Dorfman , Kerim Kalafala , Natesan Venkateswaran , Chandramouli Visweswariah
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method for performing a hierarchical statistical timing analysis of an integrated circuit (IC) chip design by abstracting one or more macros of the design. The method includes performing a statistical static timing analysis of at least one macro; performing a statistical abstraction of the macro to obtain a statistical abstract model of the macro timing characteristics; applying the statistical abstract model as the timing model for each occurrence of the macro leading to a simplified IC chip design; and performing a hierarchical statistical timing analysis of the simplified chip design. The method achieves a context aware statistical abstraction, where a generated statistical abstract model is instantiated for each macro of the chip during statistical static timing analysis at the chip level, providing a compressed and pruned statistical timing abstraction and reducing the model-size during the statistical abstraction.
摘要翻译：一种用于通过抽象设计的一个或多个宏来执行集成电路（IC）芯片设计的分层统计时序分析的方法。该方法包括执行至少一个宏的统计静态时序分析; 执行宏的统计抽象以获得宏定时特征的统计抽象模型; 将统计抽象模型应用于宏观出现的时序模型，从而实现简化的IC芯片设计; 并执行简化芯片设计的分层统计时序分析。该方法实现上下文感知统计抽象，其中在芯片级的统计静态时序分析期间为芯片的每个宏实例化生成的统计抽象模型，提供压缩和修剪的统计时序抽象并且在统计期间减小模型大小抽象。

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