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1. 发明授权

US07263566B2 Method and apparatus of reducing transfer latency in an SOC interconnect 有权
标题翻译：减少SOC互连中传输延迟的方法和装置
公开(公告)号：US07263566B2
公开(公告)日：2007-08-28
申请号：US11027532
申请日：2004-12-30
申请人： J. Prakash Subramaniam Ganasan , Perry Willmann Remaklus, Jr.
发明人： J. Prakash Subramaniam Ganasan , Perry Willmann Remaklus, Jr.
IPC分类号： G06F13/366
CPC分类号： G06F13/364
摘要： Embodiments of the invention are directed to a method and apparatus for reducing transfer latency in a system on a chip, the system on a chip comprising a bus master, a bus slave and an arbiter, wherein the bus master, bus slave and arbiter are in electronic communication therebetween. A request is transmitted from the bus master to the arbiter, wherein a priority signal is associated with a latency requirement. The arbiter reviews the latency requirement prior to transmitting the request to the bus slave and determines whether to elevate the priority signal. The request signal is then transmitted from the arbiter to the bus slave. The bus slave fulfills the request and transmits a response to the request, wherein the transmission includes the priority signal.
摘要翻译：本发明的实施例涉及用于减少芯片上的系统中的传输等待时间的方法和装置，该芯片上的系统包括总线主机，总线从机和仲裁器，其中总线主机，总线从机和仲裁器处于电子通讯。请求从总线主机发送到仲裁器，其中优先级信号与等待时间要求相关联。仲裁器在将请求发送到总线从设备之前审查延迟要求，并确定是否提升优先级信号。然后，请求信号从仲裁器发送到总线从站。总线从站满足请求并发送对请求的响应，其中传输包括优先级信号。

2. 发明授权

US07246188B2 Flow control method to improve bus utilization in a system-on-a-chip integrated circuit 有权
标题翻译：流量控制方法，以提高系统级芯片集成电路中的总线利用率
公开(公告)号：US07246188B2
公开(公告)日：2007-07-17
申请号：US11055922
申请日：2005-02-10
申请人： J. Prakash Subramaniam Ganasan , Perry Willmann Remaklus, Jr.
发明人： J. Prakash Subramaniam Ganasan , Perry Willmann Remaklus, Jr.
IPC分类号： G06F13/14
CPC分类号： G06F13/4022 , G06F2213/0038 , Y02D10/14 , Y02D10/151
摘要： A system-on-chip (SoC) integrated circuit (IC) has reduced bus contention and improved bus utilization. The SoC IC includes a bus controller. Masters interconnected with the bus controller issue requests for data and receive requested data in response to the requests. Slaves interconnected with the bus controller receive the requests for data and provide the requested data to the requesting masters. Control signals issued by the bus controller indicate to each slave which masters are not ready to receive the data it requested from that slave. The slaves delay transferring data to any masters that are not ready for the requested data, and provide data to different masters that are ready to receive the data they requested from the slaves.
摘要翻译：片上系统（SoC）集成电路（IC）减少了总线竞争并改善了总线利用率。 SoC IC包括总线控制器。与总线控制器互连的主站响应请求，发出数据请求并接收所请求的数据。与总线控制器互连的从站接收数据请求，并将请求的数据提供给请求主机。由总线控制器发出的控制信号向每个从站指示哪些主机尚未准备好接收从该从站请求的数据。从站延迟将数据传输到未准备好请求的数据的任何主站，并向准备好接收从从站请求的数据的不同主站提供数据。

3. 发明申请

US20060149874A1 Method and apparatus of reducing transfer latency in an SOC interconnect 有权
标题翻译：减少SOC互连中传输延迟的方法和装置
公开(公告)号：US20060149874A1
公开(公告)日：2006-07-06
申请号：US11027532
申请日：2004-12-30
申请人： J. Prakash Subramaniam Ganasan , Perry Willmann Remaklus
发明人： J. Prakash Subramaniam Ganasan , Perry Willmann Remaklus
IPC分类号： G06F13/00
CPC分类号： G06F13/364
摘要： Embodiments of the invention are directed to a method and apparatus for reducing transfer latency in a system on a chip, the system on a chip comprising a bus master, a bus slave and an arbiter, wherein the bus master, bus slave and arbiter are in electronic communication therebetween. A request is transmitted from the bus master to the arbiter, wherein a priority signal is associated with a latency requirement. The arbiter reviews the latency requirement prior to transmitting the request to the bus slave and determines whether to elevate the priority signal. The request signal is then transmitted from the arbiter to the bus slave. The bus slave fulfills the request and transmits a response to the request, wherein the transmission includes the priority signal.
摘要翻译：本发明的实施例涉及一种用于减少芯片上的系统中的传输等待时间的方法和装置，该芯片上的系统包括总线主机，总线从机和仲裁器，其中总线主机，总线从机和仲裁器处于电子通讯。请求从总线主机发送到仲裁器，其中优先级信号与等待时间要求相关联。仲裁器在将请求发送到总线从设备之前审查延迟要求，并确定是否提升优先级信号。然后，请求信号从仲裁器发送到总线从站。总线从站满足请求并发送对请求的响应，其中传输包括优先级信号。

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