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1. 发明授权

US08122187B2 Refreshing dynamic volatile memory 有权
标题翻译：刷新动态易失性内存
公开(公告)号：US08122187B2
公开(公告)日：2012-02-21
申请号：US11150649
申请日：2005-06-10
申请人： Robert Michael Walker , Perry Willmann Remaklus, Jr.
发明人： Robert Michael Walker , Perry Willmann Remaklus, Jr.
IPC分类号： G06F12/00
CPC分类号： G11C11/406
摘要： A memory system, and process for refreshing the memory, is disclosed. The memory system includes memory, a temperature sensor configured to measure the temperature of the memory, and a memory controller configured to refresh the memory at a refresh rate, the refresh rate being controlled as a function of the temperature measured by the temperature sensor.
摘要翻译：公开了一种存储器系统和用于刷新存储器的过程。存储器系统包括存储器，被配置为测量存储器的温度的温度传感器以及被配置为刷新刷新速率的存储器的存储器控制器，该刷新率根据由温度传感器测量的温度来控制。

2. 发明申请

US20090089515A1 Memory Controller for Performing Memory Block Initialization and Copy 审中-公开
标题翻译：用于执行存储器块初始化和复制的存储器控制器
公开(公告)号：US20090089515A1
公开(公告)日：2009-04-02
申请号：US11865970
申请日：2007-10-02
申请人： Gerald Paul Michalak , Richard Gerard Hofmann , Perry Willmann Remaklus, JR.
发明人： Gerald Paul Michalak , Richard Gerard Hofmann , Perry Willmann Remaklus, JR.
IPC分类号： G06F12/00
CPC分类号： G06F13/1668
摘要： A memory controller and methods for performing memory block initialization and copy functions with reduced bus traffic are disclosed. The memory controller can perform the memory initialization by receiving a start address of a memory, an end address of the memory and a fill value. The fill value is then written from the memory controller to the memory in a fill range of arbitrary length defined by the start address and end address.
摘要翻译：公开了一种用于执行具有减少的总线流量的存储器块初始化和复制功能的存储器控制器和方法。存储器控制器可以通过接收存储器的起始地址，存储器的结束地址和填充值来执行存储器初始化。然后将填充值从存储器控制器写入到由起始地址和结束地址定义的任意长度的填充范围内的存储器中。

3. 发明授权

US07586805B2 Method and system for providing directed bank refresh for volatile memories 有权
标题翻译：为易失性存储器提供定向库刷新的方法和系统
公开(公告)号：US07586805B2
公开(公告)日：2009-09-08
申请号：US11374838
申请日：2006-03-14
申请人： Perry Willmann Remaklus, Jr. , Robert Michael Walker
发明人： Perry Willmann Remaklus, Jr. , Robert Michael Walker
IPC分类号： G11C7/00
CPC分类号： G11C11/40611 , G11C11/406 , G11C11/40618
摘要： A memory system is provided. The memory system includes a volatile memory having a number of banks and a memory controller configured to control the volatile memory to engage in an auto-refresh mode or a self-refresh mode. The memory controller is further configured to direct the volatile memory to perform an auto-refresh operation on a target bank. The remaining banks are available for access while the auto-refresh operation is being performed on the target bank.
摘要翻译：提供了一种存储系统。存储器系统包括具有多个存储体的易失性存储器和被配置为控制易失性存储器参与自动刷新模式或自刷新模式的存储器控制器。存储器控制器还被配置为引导易失性存储器对目标存储体执行自动刷新操作。在目标银行执行自动刷新操作时，剩余的银行可以访问。

4. 发明授权

US07263566B2 Method and apparatus of reducing transfer latency in an SOC interconnect 有权
标题翻译：减少SOC互连中传输延迟的方法和装置
公开(公告)号：US07263566B2
公开(公告)日：2007-08-28
申请号：US11027532
申请日：2004-12-30
申请人： J. Prakash Subramaniam Ganasan , Perry Willmann Remaklus, Jr.
发明人： J. Prakash Subramaniam Ganasan , Perry Willmann Remaklus, Jr.
IPC分类号： G06F13/366
CPC分类号： G06F13/364
摘要： Embodiments of the invention are directed to a method and apparatus for reducing transfer latency in a system on a chip, the system on a chip comprising a bus master, a bus slave and an arbiter, wherein the bus master, bus slave and arbiter are in electronic communication therebetween. A request is transmitted from the bus master to the arbiter, wherein a priority signal is associated with a latency requirement. The arbiter reviews the latency requirement prior to transmitting the request to the bus slave and determines whether to elevate the priority signal. The request signal is then transmitted from the arbiter to the bus slave. The bus slave fulfills the request and transmits a response to the request, wherein the transmission includes the priority signal.
摘要翻译：本发明的实施例涉及用于减少芯片上的系统中的传输等待时间的方法和装置，该芯片上的系统包括总线主机，总线从机和仲裁器，其中总线主机，总线从机和仲裁器处于电子通讯。请求从总线主机发送到仲裁器，其中优先级信号与等待时间要求相关联。仲裁器在将请求发送到总线从设备之前审查延迟要求，并确定是否提升优先级信号。然后，请求信号从仲裁器发送到总线从站。总线从站满足请求并发送对请求的响应，其中传输包括优先级信号。

5. 发明授权

US07953921B2 Directed auto-refresh synchronization 有权
标题翻译：定向自动刷新同步
公开(公告)号：US07953921B2
公开(公告)日：2011-05-31
申请号：US11115915
申请日：2005-04-27
申请人： Robert Michael Walker , Perry Willmann Remaklus, Jr.
发明人： Robert Michael Walker , Perry Willmann Remaklus, Jr.
IPC分类号： G06F13/00
CPC分类号： G06F13/1636 , G11C11/406
摘要： In a directed auto-refresh (DARF) mode, refresh commands are issued by a controller, and refresh row and bank addresses are maintained internally to a memory module. A bank address counter internal to the memory is initialized to a first predetermined value upon entering DARF mode. The memory refreshes the currently addressed bank in response to a DARF command, and increments the bank address counter in a predetermined sequence. The controller tracks the bank address, and may issue one or more memory access commands while a DARF operation is being performed, if the memory access and the refresh are directed to different banks. Upon exiting a self-refresh mode, the bank address counter assumes a second predetermined value. The second predetermined value may be fixed, or may be n+1, where n is the value of the bank address counter when self-refresh mode is initiated.
摘要翻译：在定向自动刷新（DARF）模式下，控制器发出刷新命令，刷新行和存储区地址在内部维护到存储器模块。进入DARF模式时，存储器内部的存储器地址计数器被初始化为第一预定值。存储器响应于DARF命令刷新当前寻址的存储体，并以预定的顺序递增存储体地址计数器。如果存储器访问和刷新被引导到不同的存储体，则控制器跟踪存储体地址，并且可以在执行DARF操作时发出一个或多个存储器访问命令。在退出自刷新模式时，银行地址计数器采取第二预定值。第二预定值可以是固定的，或者可以是n + 1，其中n是当启动自刷新模式时存储体地址计数器的值。

6. 发明申请

US20110055495A1 Memory Controller Page Management Devices, Systems, and Methods 审中-公开
标题翻译：内存控制器页面管理设备，系统和方法
公开(公告)号：US20110055495A1
公开(公告)日：2011-03-03
申请号：US12549635
申请日：2009-08-28
申请人： Barry Joe Wolford , Perry Willmann Remaklus, JR.
发明人： Barry Joe Wolford , Perry Willmann Remaklus, JR.
IPC分类号： G06F12/00 , G06F12/10
CPC分类号： G06F13/1694
摘要： Memory controller page management devices, systems, and methods are disclosed. In one embodiment, a memory controller is configured to access memory in response to a memory access request. The memory controller is configured to apply a page management policy to either leave open or close a memory page based on at least identification information of a requestor. In this manner, a memory page management policy can be applied by the memory controller to optimize memory access times and reduce latency based on the identification of the requestor. For example, the requestor may be associated with sequential or series of memory access requests to the same memory such that a leave open page management policy would be optimal for reduced memory access times. As another example, the requestor may be associated with memory access requests to random memory pages such that a close page management policy would be optimal for reduced memory access times.
摘要翻译：公开了内存控制器页面管理设备，系统和方法。在一个实施例中，存储器控制器被配置为响应于存储器访问请求访问存储器。存储器控制器被配置为应用页面管理策略来至少基于请求者的标识信息来打开或关闭存储器页面。以这种方式，存储器控制器可以应用存储器页面管理策略以优化存储器访问时间并且基于请求者的标识来减少等待时间。例如，请求者可以与对相同存储器的顺序或一系列存储器访问请求相关联，使得离开打开页面管理策略对于减少的存储器访问时间将是最佳的。作为另一示例，请求者可以与对随机存储器页面的存储器访问请求相关联，使得关闭页面管理策略对于减少的存储器访问时间来说将是最佳的。

7. 发明授权

US07583552B2 Method and system for providing independent bank refresh for volatile memories 有权
标题翻译：为易失性存储器提供独立的刷新刷新方法和系统
公开(公告)号：US07583552B2
公开(公告)日：2009-09-01
申请号：US11623366
申请日：2007-01-16
申请人： Perry Willmann Remaklus, Jr. , Robert Michael Walker
发明人： Perry Willmann Remaklus, Jr. , Robert Michael Walker
IPC分类号： G11C7/00
CPC分类号： G06F13/1636 , G11C11/406 , G11C11/40611 , G11C11/40618 , Y02D10/14
摘要： A memory system is provided. The memory system includes a volatile memory having a number of banks, each bank having a number of rows, and a memory controller configured to direct the volatile memory to engage in an auto-refresh mode, the memory controller further configured to provide a target bank address to the volatile memory. The volatile memory is configured to perform an auto-refresh operation in the auto-refresh mode, the auto-refresh operation being performed on a target bank identified by the target bank address. Remaining banks in the plurality of banks other than the target bank are available for memory access while the auto-refresh operation is being performed on the target bank.
摘要翻译：提供了一种存储系统。存储器系统包括具有多个存储体的易失性存储器，每个存储体具有多个行，以及存储器控制器，其被配置为引导易失性存储器参与自动刷新模式，存储器控制器还被配置为提供目标存储体地址到易失性存储器。易失性存储器被配置为在自动刷新模式下执行自动刷新操作，在由目标库地址识别的目标库上执行自动刷新操作。目标银行以外的多个银行中的剩余银行可用于存储器访问，同时对目标银行进行自动刷新操作。

8. 发明授权

US07246188B2 Flow control method to improve bus utilization in a system-on-a-chip integrated circuit 有权
标题翻译：流量控制方法，以提高系统级芯片集成电路中的总线利用率
公开(公告)号：US07246188B2
公开(公告)日：2007-07-17
申请号：US11055922
申请日：2005-02-10
申请人： J. Prakash Subramaniam Ganasan , Perry Willmann Remaklus, Jr.
发明人： J. Prakash Subramaniam Ganasan , Perry Willmann Remaklus, Jr.
IPC分类号： G06F13/14
CPC分类号： G06F13/4022 , G06F2213/0038 , Y02D10/14 , Y02D10/151
摘要： A system-on-chip (SoC) integrated circuit (IC) has reduced bus contention and improved bus utilization. The SoC IC includes a bus controller. Masters interconnected with the bus controller issue requests for data and receive requested data in response to the requests. Slaves interconnected with the bus controller receive the requests for data and provide the requested data to the requesting masters. Control signals issued by the bus controller indicate to each slave which masters are not ready to receive the data it requested from that slave. The slaves delay transferring data to any masters that are not ready for the requested data, and provide data to different masters that are ready to receive the data they requested from the slaves.
摘要翻译：片上系统（SoC）集成电路（IC）减少了总线竞争并改善了总线利用率。 SoC IC包括总线控制器。与总线控制器互连的主站响应请求，发出数据请求并接收所请求的数据。与总线控制器互连的从站接收数据请求，并将请求的数据提供给请求主机。由总线控制器发出的控制信号向每个从站指示哪些主机尚未准备好接收从该从站请求的数据。从站延迟将数据传输到未准备好请求的数据的任何主站，并向准备好接收从从站请求的数据的不同主站提供数据。

9. 发明授权

US07184350B2 Method and system for providing independent bank refresh for volatile memories 有权
标题翻译：为易失性存储器提供独立的刷新刷新方法和系统
公开(公告)号：US07184350B2
公开(公告)日：2007-02-27
申请号：US10982691
申请日：2004-11-05
申请人： Perry Willmann Remaklus, Jr. , Robert Michael Walker
发明人： Perry Willmann Remaklus, Jr. , Robert Michael Walker
IPC分类号： G11C7/00
CPC分类号： G06F13/1636 , G11C11/406 , G11C11/40611 , G11C11/40618 , Y02D10/14
摘要： A memory system is provided. The memory system includes a volatile memory having a number of banks, each bank having a number of rows, and a memory controller configured to direct the volatile memory to engage in an auto-refresh mode, the memory controller further configured to provide a target bank address to the volatile memory. The volatile memory is configured to perform an auto-refresh operation in the auto-refresh mode, the auto-refresh operation being performed on a target bank identified by the target bank address. Remaining banks in the plurality of banks other than the target bank are available for memory access while the auto-refresh operation is being performed on the target bank.
摘要翻译：提供了一种存储系统。存储器系统包括具有多个存储体的易失性存储器，每个存储体具有多个行，以及存储器控制器，其被配置为引导易失性存储器参与自动刷新模式，存储器控制器还被配置为提供目标存储体地址到易失性存储器。易失性存储器被配置为在自动刷新模式下执行自动刷新操作，在由目标库地址识别的目标库上执行自动刷新操作。目标银行以外的多个银行中的剩余银行可用于存储器访问，同时对目标银行进行自动刷新操作。

10. 发明授权

US07088633B2 Method and system for providing seamless self-refresh for directed bank refresh in volatile memories 有权
标题翻译：用于为易失性存储器中的定向库刷新提供无缝自刷新的方法和系统
公开(公告)号：US07088633B2
公开(公告)日：2006-08-08
申请号：US10982277
申请日：2004-11-05
申请人： Perry Willmann Remaklus, Jr. , Robert Michael Walker
发明人： Perry Willmann Remaklus, Jr. , Robert Michael Walker
IPC分类号： G11C7/00
CPC分类号： G11C11/40611 , G11C11/406
摘要： A memory system is provided. The system includes a volatile memory having a number of banks and configured to engage in one of a number of operating modes including an auto-refresh mode and a self-refresh mode, and a memory controller configured to direct the volatile memory to engage in one of the operating modes. Upon the memory controller directing the volatile memory to engage in the self-refresh mode, the memory controller is further configured to provide an entry bank address to the volatile memory, the entry bank address corresponding to the first bank that is to be refreshed during the self-refresh mode. Upon the volatile memory exiting the self-refresh mode, the volatile memory is further configured to make an exit bank address available to the memory controller, the exit bank address corresponding to the last bank that was refreshed prior to the volatile memory exiting the self-refresh mode.
摘要翻译：提供了一种存储系统。该系统包括具有多个存储体并被配置为参与包括自动刷新模式和自刷新模式的多种操作模式中的一种操作模式的易失性存储器，以及配置为引导易失性存储器参与一个的操作模式。在存储器控制器引导易失性存储器进行自刷新模式的情况下，存储器控制器进一步被配置为向易失性存储器提供入口库地址，对应于在第一存储区期间将被刷新的入口库地址自刷新模式。在易失性存储器退出自刷新模式时，易失性存储器进一步被配置为使存储器控制器可用的出库组地址，对应于在易失性存储器离开自组织之前刷新的最后一个存储体的出库组地址，刷新模式。

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