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1. 发明授权

US07615926B2 Low voltage microcavity plasma device and addressable arrays 有权
标题翻译：低电压微腔等离子体器件和可寻址阵列
公开(公告)号：US07615926B2
公开(公告)日：2009-11-10
申请号：US11811892
申请日：2007-06-12
申请人： J. Gary Eden , Sung-Jin Park , Paul A. Tchertchian , Seung Hoon Sung
发明人： J. Gary Eden , Sung-Jin Park , Paul A. Tchertchian , Seung Hoon Sung
IPC分类号： H01J17/49
CPC分类号： H01J11/12
摘要： Microcavity plasma devices and arrays of microcavity plasma devices are provided that have a reduced excitation voltage. A trigger electrode disposed proximate to a microcavity reduce the excitation voltage required between first and second electrodes to ignite a plasma in the microcavity when gas(es) or vapor(s) (or combinations thereof) are contained within the microcavity. The invention also provides symmetrical microplasma devices and arrays of microcavity plasma devices for which current waveforms are the same for each half-cycle of the voltage driving waveform. Additionally, the invention also provides devices that have standoff portions and voids that can reduce cross talk. The devices are preferably also used with a trigger electrode.
摘要翻译：提供微腔等离子体器件和微腔等离子体器件的阵列，其具有降低的激发电压。在微腔内包含气体或蒸汽（或其组合）时，靠近微腔设置的触发电极减小了第一和第二电极之间所需的激发电压，以点燃微腔中的等离子体。本发明还提供对称的微等离子体装置和微腔等离子体装置的阵列，其电流波形对于电压驱动波形的每个半周期是相同的。此外，本发明还提供了具有能够减少串扰的间隔部分和空隙的装置。这些装置优选地也与触发电极一起使用。

2. 发明申请

US20080129185A1 Low voltage microcavity plasma device and addressable arrays 有权
标题翻译：低电压微腔等离子体器件和可寻址阵列
公开(公告)号：US20080129185A1
公开(公告)日：2008-06-05
申请号：US11811892
申请日：2007-06-12
申请人： J.Gary Eden , Sung-Jin Park , Paul A. Tchertchian , Seung Hoon Sung
发明人： J.Gary Eden , Sung-Jin Park , Paul A. Tchertchian , Seung Hoon Sung
IPC分类号： H05H1/24
CPC分类号： H01J11/12
摘要： Microcavity plasma devices and arrays of microcavity plasma devices are provided that have a reduced excitation voltage. A trigger electrode disposed proximate to a microcavity reduce the excitation voltage required between first and second electrodes to ignite a plasma in the microcavity when gas(es) or vapor(s) (or combinations thereof) are contained within the microcavity. The invention also provides symmetrical microplasma devices and arrays of microcavity plasma devices for which current waveforms are the same for each half-cycle of the voltage driving waveform. Additionally, the invention also provides devices that have standoff portions and voids that can reduce cross talk. The devices are preferably also used with a trigger electrode.
摘要翻译：提供微腔等离子体器件和微腔等离子体器件的阵列，其具有降低的激发电压。在微腔内包含气体或蒸汽（或其组合）时，靠近微腔设置的触发电极减小了第一和第二电极之间所需的激发电压，以点燃微腔中的等离子体。本发明还提供对称的微等离子体装置和微腔等离子体装置的阵列，其电流波形对于电压驱动波形的每个半周期是相同的。此外，本发明还提供了具有能够减少串扰的间隔部分和空隙的装置。这些装置优选地也与触发电极一起使用。

3. 发明申请

US20130071297A1 ARRAYS OF METAL AND METAL OXIDE MICROPLASMA DEVICES WITH DEFECT FREE OXIDE 有权
标题翻译：金属和金属氧化物微孔器件与无氧氧化物的阵列
公开(公告)号：US20130071297A1
公开(公告)日：2013-03-21
申请号：US13527842
申请日：2012-06-20
申请人： J. Gary Eden , Sung-Jin Park , Jin Hoon Cho , Seung Hoon Sung , Min Hwan Kim
发明人： J. Gary Eden , Sung-Jin Park , Jin Hoon Cho , Seung Hoon Sung , Min Hwan Kim
IPC分类号： H01J37/32 , C25D11/02
CPC分类号： B01J19/0093 , B01J2219/00783 , B01J2219/00842 , B01J2219/00853 , B01J2219/00891 , C01B13/115 , C25D11/02 , C25D11/022 , C25D11/026 , C25D11/12 , C25D11/18 , C25D11/26 , H01J11/18 , H01J11/22 , H01J11/34 , H01J17/066 , H01J17/16 , H01J37/32055 , H05H2001/2412 , H05H2001/2418
摘要： A microplasma device includes a microcavity or microchannel defined at least partially within a thick metal oxide layer consisting essentially of defect free oxide. Electrodes are arranged with respect to the microcavity or microchannel to stimulate plasma generation in said microcavity or microchannel. At least one of the electrodes is encapsulated within the thick metal oxide layer. A method of fabricating a microcavity or microchannel plasma device includes anodizing a flat or gently curved or gently sloped metal substrate to form a thick layer of metal oxide consisting essentially of nanopores that are perpendicular to the surface of the metal substrate. Material removal is conducted to remove metal oxide material to form a microcavity or microchannel in the thick layer of metal oxide.
摘要翻译：微型装置包括至少部分地在基本上由无缺陷氧化物组成的厚金属氧化物层内限定的微腔或微通道。电极相对于微腔或微通道布置以刺激所述微腔或微通道中的血浆产生。至少一个电极被封装在厚的金属氧化物层内。一种制造微腔或微通道等离子体装置的方法包括阳极氧化平坦或轻柔地弯曲或缓慢倾斜的金属基底，以形成基本上由纳米孔组成的厚层，金属氧化物垂直于金属基底的表面。进行材料去除以除去金属氧化物材料以在金属氧化物的厚层中形成微腔或微通道。

4. 发明申请

US20100072893A1 ELLIPSOIDAL MICROCAVITY PLASMA DEVICES AND POWDER BLASTING FORMATION 有权
标题翻译： ELLIPSOIDAL微波等离子体装置和粉末喷砂形成
公开(公告)号：US20100072893A1
公开(公告)日：2010-03-25
申请号：US12235796
申请日：2008-09-23
申请人： J. Gary Eden , Sung-Jin Park , Seung Hoon Sung
发明人： J. Gary Eden , Sung-Jin Park , Seung Hoon Sung
IPC分类号： H01J17/49 , H01J9/24
CPC分类号： H01J65/046 , H01J9/241 , H01J11/18
摘要： The invention provides microcavity plasma devices and arrays that are formed in layers that also seal the plasma medium, i.e., gas(es) and/or vapors. No separate packaging layers are required and additional packaging can be omitted if it is desirable to do so. A preferred microcavity plasma device includes first and second thin layers that are joined together. A half ellipsoid microcavity or plurality of half ellipsoid microcavities is defined in one or both of the first and second thin layers, and electrodes are arranged with respect to the microcavity to excite a plasma within said microcavities upon application of a predetermined voltage to the electrodes. A method for forming a microcavity plasma device having a plurality of half or full ellipsoid microcavities in one or both of first and second thin layers is also provided by a preferred embodiment. The method includes defining a pattern of protective polymer on the first thin layer. Powder blasting forms half ellipsoid microcavities in the first thin layer. The second thin layer is joined to the first layer. The patterning can be conducted lithographically or can be conduced with a simple screen.
摘要翻译：本发明提供了形成为也密封等离子体介质即气体和/或蒸汽的层的微腔等离子体装置和阵列。不需要单独的包装层，如果要这样做，可以省略额外的包装。优选的微腔等离子体装置包括连接在一起的第一和第二薄层。半椭圆形微腔或多个半椭圆形微腔被限定在第一和第二薄层中的一个或两个中，并且相对于微腔布置电极，以在对电极施加预定电压时在所述微腔内激发等离子体。优选实施例也提供了一种在第一和第二薄层中的一个或两个中形成具有多个半或全椭圆形微腔的微腔等离子体装置的方法。该方法包括在第一薄层上限定保护性聚合物的图案。粉末喷射在第一薄层中形成半椭圆形微腔。第二薄层连接到第一层。图案化可以光刻地进行，或者可以用简单的屏幕进行。

5. 发明授权

US08968668B2 Arrays of metal and metal oxide microplasma devices with defect free oxide 有权
标题翻译：具有缺陷氧化物的金属和金属氧化物微质体装置阵列
公开(公告)号：US08968668B2
公开(公告)日：2015-03-03
申请号：US13527842
申请日：2012-06-20
申请人： J. Gary Eden , Sung-Jin Park , Jin Hoon Cho , Seung Hoon Sung , Min Hwan Kim
发明人： J. Gary Eden , Sung-Jin Park , Jin Hoon Cho , Seung Hoon Sung , Min Hwan Kim
IPC分类号： B01J19/08 , H01J37/32 , C25D11/02 , H01J11/18 , C25D11/12 , C25D11/18 , C25D11/26 , H01J17/16
CPC分类号： B01J19/0093 , B01J2219/00783 , B01J2219/00842 , B01J2219/00853 , B01J2219/00891 , C01B13/115 , C25D11/02 , C25D11/022 , C25D11/026 , C25D11/12 , C25D11/18 , C25D11/26 , H01J11/18 , H01J11/22 , H01J11/34 , H01J17/066 , H01J17/16 , H01J37/32055 , H05H2001/2412 , H05H2001/2418
摘要： A microplasma device of the invention includes a microcavity or microchannel defined at least partially within a thick metal oxide layer consisting essentially of defect free oxide. Electrodes are arranged with respect to the microcavity or microchannel to stimulate plasma generation in said microcavity or microchannel upon application of suitable voltage and at least one of the electrodes is encapsulated within the thick metal oxide layer. Large arrays can be formed and are highly robust as lack of microcracks in the oxide avoid dielectric breakdown.
摘要翻译：本发明的微血管装置包括至少部分地限定在基本上由无缺氧氧化物组成的厚金属氧化物层内的微腔或微通道。电极相对于微腔或微通道布置，以在施加适当电压时刺激所述微腔或微通道中的等离子体产生，并且至少一个电极被封装在厚金属氧化物层内。可以形成大阵列，并且由于在氧化物中缺少微裂纹以避免电介质击穿，因此它们具有很强的鲁棒性。

6. 发明授权

US08179032B2 Ellipsoidal microcavity plasma devices and powder blasting formation 有权
标题翻译：椭球微腔等离子体装置和粉末爆破形成
公开(公告)号：US08179032B2
公开(公告)日：2012-05-15
申请号：US12235796
申请日：2008-09-23
申请人： J. Gary Eden , Sung-Jin Park , Seung Hoon Sung
发明人： J. Gary Eden , Sung-Jin Park , Seung Hoon Sung
IPC分类号： H01J1/00 , H01J1/88
CPC分类号： H01J65/046 , H01J9/241 , H01J11/18
摘要： The invention provides microcavity plasma devices and arrays that are formed in layers that also seal the plasma medium, i.e., gas(es) and/or vapors. No separate packaging layers are required and additional packaging can be omitted if it is desirable to do so. A preferred microcavity plasma device includes first and second thin layers that are joined together. A half ellipsoid microcavity or plurality of half ellipsoid microcavities is defined in one or both of the first and second thin layers, and electrodes are arranged with respect to the microcavity to excite a plasma within said microcavities upon application of a predetermined voltage to the electrodes. A method for forming a microcavity plasma device having a plurality of half or full ellipsoid microcavities in one or both of first and second thin layers is also provided by a preferred embodiment. The method includes defining a pattern of protective polymer on the first thin layer. Powder blasting forms half ellipsoid microcavities in the first thin layer. The second thin layer is joined to the first layer. The patterning can be conducted lithographically or can be conduced with a simple screen.
摘要翻译：本发明提供了形成为也密封等离子体介质即气体和/或蒸汽的层的微腔等离子体装置和阵列。不需要单独的包装层，如果要这样做，可以省略额外的包装。优选的微腔等离子体装置包括连接在一起的第一和第二薄层。半椭圆形微腔或多个半椭圆形微腔被限定在第一和第二薄层中的一个或两个中，并且相对于微腔布置电极，以在对电极施加预定电压时在所述微腔内激发等离子体。优选实施例也提供了一种在第一和第二薄层中的一个或两个中形成具有多个半或全椭圆形微腔的微腔等离子体装置的方法。该方法包括在第一薄层上限定保护性聚合物的图案。粉末喷射在第一薄层中形成半椭圆形微腔。第二薄层连接到第一层。图案化可以光刻地进行，或者可以用简单的屏幕进行。

7. 发明授权

US09634007B2 Trench confined epitaxially grown device layer(s) 有权
公开(公告)号：US09634007B2
公开(公告)日：2017-04-25
申请号：US14302350
申请日：2014-06-11
申请人： Ravi Pillarisetty , Seung Hoon Sung , Niti Goel , Jack T. Kavalieros , Sansaptak Dasgupta , Van H. Le , Willy Rachmady , Marko Radosavljevic , Gilbert Dewey , Han Wui Then , Niloy Mukherjee , Matthew V. Metz , Robert S. Chau
发明人： Ravi Pillarisetty , Seung Hoon Sung , Niti Goel , Jack T. Kavalieros , Sansaptak Dasgupta , Van H. Le , Willy Rachmady , Marko Radosavljevic , Gilbert Dewey , Han Wui Then , Niloy Mukherjee , Matthew V. Metz , Robert S. Chau
IPC分类号： H01L29/66 , H01L29/78 , H01L21/02 , H01L21/762 , H01L27/092 , H01L21/8258 , H01L29/423 , H01L29/786 , B82Y10/00 , B82Y40/00 , H01L29/775 , H01L29/06 , H01L21/8238
CPC分类号： H01L21/845 , B82Y10/00 , B82Y40/00 , H01L21/02639 , H01L21/823807 , H01L21/8258 , H01L27/092 , H01L27/1211 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/6653 , H01L29/66795 , H01L29/6681 , H01L29/775 , H01L29/78 , H01L29/785 , H01L29/7853 , H01L29/78696
摘要： Trench-confined selective epitaxial growth process in which epitaxial growth of a semiconductor device layer proceeds within the confines of a trench. In embodiments, a trench is fabricated to include a pristine, planar semiconductor seeding surface disposed at the bottom of the trench. Semiconductor regions around the seeding surface may be recessed relative to the seeding surface with Isolation dielectric disposed there on to surround the semiconductor seeding layer and form the trench. In embodiments to form the trench, a sacrificial hardmask fin may be covered in dielectric which is then planarized to expose the hardmask fin, which is then removed to expose the seeding surface. A semiconductor device layer is formed from the seeding surface through selective heteroepitaxy. In embodiments, non-planar devices are formed from the semiconductor device layer by recessing a top surface of the isolation dielectric. In embodiments, non-planar devices CMOS devices having high carrier mobility may be made from the semiconductor device layer.

8. 发明申请

US20160233344A1 DEEP GATE-ALL-AROUND SEMICONDUCTOR DEVICE HAVING GERMANIUM OR GROUP III-V ACTIVE LAYER 审中-公开
公开(公告)号：US20160233344A1
公开(公告)日：2016-08-11
申请号：US15134093
申请日：2016-04-20
申请人： Ravi Pillarisetty , Willy Rachmady , Van H. Le , Seung Hoon Sung , Jessica S. Kachian , Jack T. Kavalieros , Han Wui Then , Gilbert Dewey , Marko Radosavljevic , Benjamin Chu-Kung , Niloy Mukherjee
发明人： Ravi Pillarisetty , Willy Rachmady , Van H. Le , Seung Hoon Sung , Jessica S. Kachian , Jack T. Kavalieros , Han Wui Then , Gilbert Dewey , Marko Radosavljevic , Benjamin Chu-Kung , Niloy Mukherjee
IPC分类号： H01L29/786 , H01L29/423 , H01L29/66 , H01L29/06
CPC分类号： H01L29/78609 , H01L29/0653 , H01L29/0673 , H01L29/0676 , H01L29/165 , H01L29/205 , H01L29/42392 , H01L29/66742 , H01L29/785 , H01L29/78606 , H01L29/78618 , H01L29/78681 , H01L29/78684 , H01L29/78696
摘要： Deep gate-all-around semiconductor devices having germanium or group III-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.

9. 发明申请

US20150349077A1 DEEP GATE-ALL-AROUND SEMICONDUCTOR DEVICE HAVING GERMANIUM OR GROUP III-V ACTIVE LAYER 审中-公开
标题翻译：具有锗或III-V族活性层的深层栅全绝缘半导体器件
公开(公告)号：US20150349077A1
公开(公告)日：2015-12-03
申请号：US14821561
申请日：2015-08-07
申请人： Ravi Pillarisetty , Willy Rachmady , Van H. Le , Seung Hoon Sung , Jessica S. Kachian , Jack T. Kavalieros , Han Wui Then , Gilbert Dewey , Marko Radosavljevic , Benjamin Chu-Kung , Niloy Mukherjee
发明人： Ravi Pillarisetty , Willy Rachmady , Van H. Le , Seung Hoon Sung , Jessica S. Kachian , Jack T. Kavalieros , Han Wui Then , Gilbert Dewey , Marko Radosavljevic , Benjamin Chu-Kung , Niloy Mukherjee
IPC分类号： H01L29/423 , H01L29/205 , H01L29/786 , H01L29/165 , H01L29/06
CPC分类号： H01L29/78609 , H01L29/0653 , H01L29/0673 , H01L29/0676 , H01L29/165 , H01L29/205 , H01L29/42392 , H01L29/66742 , H01L29/785 , H01L29/78606 , H01L29/78618 , H01L29/78681 , H01L29/78684 , H01L29/78696
摘要： Deep gate-all-around semiconductor devices having germanium or group III-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.
摘要翻译：描述具有锗或III-V族有源层的深栅极全面半导体器件。例如，非平面半导体器件包括设置在衬底上的异质结构。异质结构包括不同组成的上层和下层之间的异质结。有源层设置在杂结构上方，并且具有与异质结构的上层和下层不同的组成。栅电极堆叠设置在有源层的沟道区上并完全包围有源层的沟道区，并且设置在上层中的沟槽中，并且至少部分地设置在异质结构的下层中。源极和漏极区域设置在栅电极堆叠的任一侧上的有源层和上层中，而不是在下层中。

10. 发明授权

US08765563B2 Trench confined epitaxially grown device layer(s) 失效
标题翻译：沟槽限制外延生长的器件层
公开(公告)号：US08765563B2
公开(公告)日：2014-07-01
申请号：US13630527
申请日：2012-09-28
申请人： Ravi Pillarisetty , Seung Hoon Sung , Niti Goel , Jack T. Kavalieros , Sansaptak Dasgupta , Van H. Le , Willy Rachmady , Marko Radosavljevic , Gilbert Dewey , Han Wui Then , Niloy Mukherjee , Matthew V. Metz , Robert S. Chau
发明人： Ravi Pillarisetty , Seung Hoon Sung , Niti Goel , Jack T. Kavalieros , Sansaptak Dasgupta , Van H. Le , Willy Rachmady , Marko Radosavljevic , Gilbert Dewey , Han Wui Then , Niloy Mukherjee , Matthew V. Metz , Robert S. Chau
IPC分类号： H01L21/00 , H01L21/311 , H01L21/8222 , H01L21/30 , H01L21/20 , H01L29/15
CPC分类号： H01L21/845 , B82Y10/00 , B82Y40/00 , H01L21/02639 , H01L21/823807 , H01L21/8258 , H01L27/092 , H01L27/1211 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/6653 , H01L29/66795 , H01L29/6681 , H01L29/775 , H01L29/78 , H01L29/785 , H01L29/7853 , H01L29/78696
摘要： Trench-confined selective epitaxial growth process in which epitaxial growth of a semiconductor device layer proceeds within the confines of a trench. In embodiments, a trench is fabricated to include a pristine, planar semiconductor seeding surface disposed at the bottom of the trench. Semiconductor regions around the seeding surface may be recessed relative to the seeding surface with Isolation dielectric disposed there on to surround the semiconductor seeding layer and form the trench. In embodiments to form the trench, a sacrificial hardmask fin may be covered in dielectric which is then planarized to expose the hardmask fin, which is then removed to expose the seeding surface. A semiconductor device layer is formed from the seeding surface through selective heteroepitaxy. In embodiments, non-planar devices are formed from the semiconductor device layer by recessing a top surface of the isolation dielectric. In embodiments, non-planar devices CMOS devices having high carrier mobility may be made from the semiconductor device layer.
摘要翻译：沟槽限制的选择性外延生长工艺，其中半导体器件层的外延生长在沟槽的范围内进行。在实施例中，制造沟槽以包括设置在沟槽底部的原始平面半导体晶种表面。接种表面周围的半导体区域可以相对于接种表面凹陷，其中隔离电介质设置在其上以包围半导体晶种层并形成沟槽。在形成沟槽的实施例中，牺牲性硬掩模翅片可以被覆盖在电介质中，然后将其平坦化以暴露硬掩模翅片，然后将其去除以暴露接种表面。通过选择性异质外延从种子表面形成半导体器件层。在实施例中，通过使隔离电介质的顶表面凹陷，从半导体器件层形成非平面器件。在实施例中，可以从半导体器件层制造具有高载流子迁移率的非平面器件CMOS器件。

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