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    • 1. 发明申请
    • INTEGRATED CIRCUIT POWER CONSUMPTION CALCULATING APPARATUS AND PROCESSING METHOD
    • 集成电路功耗计算设备和处理方法
    • US20120249230A1
    • 2012-10-04
    • US13493432
    • 2012-06-11
    • Itsumi SUGIYAMATomohiro TANAKA
    • Itsumi SUGIYAMATomohiro TANAKA
    • H01L25/00
    • G06F17/5022G06F2217/78H01L2924/0002H01L2924/00
    • An integrated circuit power consumption calculating apparatus obtains power consumption of an integrated circuit by outputting circuit component transistor connection information of each of circuit components after setting a group of transistors connected via a source terminal/drain terminal of a transistor within each cell of an integrated circuit, by outputting circuit component logic model information after extracting a logic for each of the circuit components from the circuit component transistor connection information information, by obtaining power information (circuit component power information) of each signal transition state of an input/output terminal for each of the circuit components based on the circuit component transistor connection information information, by generating signal terminal transition information with a logic simulation performed for each of the circuit components of the integrated circuit, and by obtaining power consumption in a signal transition of an input/output terminal of each of the circuit components.
    • 集成电路功耗计算装置通过在设置通过集成电路的每个单元内的晶体管的源极/漏极连接的晶体管组之后输出电路部件的电路成分晶体管连接信息来获得集成电路的功耗 通过从电路部件晶体管连接信息信息中提取每个电路部件的逻辑,通过为每个信号获取输入/输出端子的每个信号转换状态的电源信息(电路部件功率信息),输出电路部件逻辑模型信息 基于电路元件晶体管连接信息信息的电路元件,通过对集成电路的每个电路元件执行的逻辑模拟产生信号端子转移信息,并且通过获得inp的信号转换中的功率消耗 每个电路组件的输出/输出端子。
    • 3. 发明申请
    • SELECTOR CIRCUIT AND PROCESSOR SYSTEM
    • 选择器电路和处理器系统
    • US20120098586A1
    • 2012-04-26
    • US13238095
    • 2011-09-21
    • Tomohiro TANAKA
    • Tomohiro TANAKA
    • H03K17/56
    • G11C8/08G11C8/10H03K17/56H03K17/693H03K19/096H03K19/0963
    • A selector circuit includes a plurality of first selection circuits each configured to select one of plural input signals on the basis of a first selection control signal and to output a first output signal and a second selection circuit configured to select one of the first output signals on the basis of a second selection control signal. Each of the first selection circuits includes a charging circuit configured to charge a first node by electrically connecting the first node to a first voltage in a first period, and a discharge control circuit configured to control, on the basis of the first selection control signal, the input signals and the second selection control signal, whether to discharge the charged first node by electrically connecting the first node to a second voltage source having a potential lower than the first voltage source in a second period following the first period.
    • 选择器电路包括多个第一选择电路,每个第一选择电路被配置为基于第一选择控制信号选择多个输入信号中的一个,并输出第一输出信号和第二选择电路,其被配置为选择第一输出信号之一 第二选择控制信号的基础。 每个第一选择电路包括充电电路,其被配置为通过在第一周期中将第一节点电连接到第一电压来对第一节点进行充电;以及放电控制电路,被配置为基于第一选择控制信号, 所述输入信号和所述第二选择控制信号是否在所述第一周期之后的第二周期期间通过将所述第一节点电连接到具有低于所述第一电压源的电位的第二电压源来对所充电的第一节点进行放电。
    • 4. 发明申请
    • ARITHMETIC PROCESSING UNIT
    • 算术处理单元
    • US20080229080A1
    • 2008-09-18
    • US12037395
    • 2008-02-26
    • Ryuji KANTomohiro TANAKAToshio YOSHIDA
    • Ryuji KANTomohiro TANAKAToshio YOSHIDA
    • G06F9/302
    • G06F9/30043G06F9/30076G06F9/30098G06F9/30101G06F9/3012G06F9/30127G06F9/3824G06F9/3826G06F9/384G06F9/3842G06F9/3867G06F9/462
    • An arithmetic processing unit includes a register file provided with multiple register windows, an arithmetic executor executes an instruction with data retained in the register file as an operand, and a current window pointer which retains address information specifying a register window which becomes a current window, and a controller. The controller controls the address information retained by the current window pointer is updated, when a window switching instruction for indicating switching of the current window has been decoded. The arithmetic executor reads data in a first register window specified by the address information before being updated and data in a second register window specified by the updated address information from the register file, after the decoding of said window switching instruction has been started until commit of the window switching instruction is started.
    • 算术处理单元包括具有多个寄存器窗口的寄存器文件,算术执行器执行具有作为操作数保留在寄存器堆中的数据的指令,以及保持指定成为当前窗口的寄存器窗口的地址信息的当前窗口指针, 和控制器。 当用于指示当前窗口的切换的窗口切换指令已被解码时,控制器控制由当前窗口指针保留的地址信息被更新。 算术执行器在所述窗口切换指令的解码已经开始直到所述窗口切换指令的解码之后,在被更新之前由地址信息指定的第一寄存器窗口中的数据和由所述更新的地址信息由所述寄存器文件指定的第二寄存器窗口中的数据进行读取 窗口切换指令开始。