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1. 发明申请

US20110314323A1 SEMICONDUCTOR DEVICE AND DATA PROCESSOR 有权
标题翻译：半导体器件和数据处理器
公开(公告)号：US20110314323A1
公开(公告)日：2011-12-22
申请号：US13220747
申请日：2011-08-30
申请人： Yoshihiko HOTTA , Seiichi SAITO , Hiroyuki HAMASAKI , Hirotaka HARA , Itaru NONOMURA
发明人： Yoshihiko HOTTA , Seiichi SAITO , Hiroyuki HAMASAKI , Hirotaka HARA , Itaru NONOMURA
IPC分类号： G06F1/12
CPC分类号： G06F1/3253 , G06F1/3237 , Y02D10/128 , Y02D10/151
摘要： To improve the speed of accessing a low-speed circuit block from a high-speed circuit block without significantly increasing power consumption.In a data processor having a bus controller that performs timing control of access from the CPU operated in synchronization with a high-speed first clock signal to a peripheral circuit operated in synchronization with a low-speed second clock signal, a timing control circuit is provided between the peripheral circuit and the bus controller, and the bus controller causes, in response to a read instruction from the peripheral circuit, the timing control circuit to output data held by the peripheral circuit to the bus controller in synchronization with the cycle of the high-speed clock signal, causes the timing control circuit to start, in response to a write instruction directed to the peripheral circuit, writing into the peripheral circuit in synchronization with the cycle of the high-speed clock signal, and terminates the writing in synchronization with the cycle of the low-speed clock signal.
摘要翻译：提高从高速电路块访问低速电路块的速度，而不会显着增加功耗。在具有总线控制器的数据处理器中，总线控制器执行与高速第一时钟信号同步操作的CPU的访问定时控制到与低速第二时钟信号同步操作的外围电路，提供定时控制电路在外围电路和总线控制器之间，并且总线控制器响应于来自外围电路的读取指令而导致定时控制电路将周边电路保持的数据与高速的周期同步地传送到总线控制器速度时钟信号，使定时控制电路响应于指向外围电路的写指令而启动，与高速时钟信号的周期同步地写入外围电路，并且与低速时钟信号的周期。

2. 发明申请

US20110320660A1 INFORMATION PROCESSING DEVICE 有权
标题翻译：信息处理设备
公开(公告)号：US20110320660A1
公开(公告)日：2011-12-29
申请号：US13170179
申请日：2011-06-27
申请人： Hirotaka HARA , Tatsuya Kamei , Takahiro Irita
发明人： Hirotaka HARA , Tatsuya Kamei , Takahiro Irita
IPC分类号： G06F13/36
CPC分类号： G06F13/362
摘要： To improve processing performance of an information processing device as a whole by controlling priority in units of processes.There are provided a bus for data transfer and a plurality of function modules each having a processing function performing processing in units of processes and capable of issuing a data transfer request for the bus. Further, there is provided a process identification information holing unit capable of holding process identification information set for each of the processes in association with the function module performing processing of the process. Furthermore, there is provided a bus arbiter determining a priority order of processing for each piece of the corresponding process identification information for each data transfer request from the function module and arbitrating contention of data transfer requests for the bus according to the priority order. Processing performance is improved by performing priority order control in units of processes.
摘要翻译：通过以进程为单位控制优先级来提高信息处理设备整体的处理性能。提供了一种用于数据传送的总线和多个功能模块，每个功能模块具有处理功能，其以处理为单位执行处理，并能够发出对总线的数据传输请求。此外，提供一种能够与执行处理的处理的功能模块相关联地保持针对每个处理设置的处理识别信息的处理识别信息挖掘单元。此外，提供了一个总线仲裁器，其根据优先级顺序确定来自功能模块的每个数据传输请求的每个相应处理标识信息的处理优先级顺序和对总线的数据传输请求的争用。通过以进程为单位执行优先顺序控制来提高处理性能。

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