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1. 发明授权

US4303653A Organic phosphoric acid ester derivatives, a process for preparing the same and insecticidal, miticidal or nematocidal compositions containing the same 失效
标题翻译：有机磷酸酯衍生物，其制备方法和含有它们的杀虫，杀螨或杀线虫组合物
公开(公告)号：US4303653A
公开(公告)日：1981-12-01
申请号：US163662
申请日：1981-06-27
申请人： Isao Chiyomaru , Hidetoshi Sugiyama , Koyata Niita , Kunihiko Fujimori , Tadayoshi Hirano , Osamu Tada
发明人： Isao Chiyomaru , Hidetoshi Sugiyama , Koyata Niita , Kunihiko Fujimori , Tadayoshi Hirano , Osamu Tada
IPC分类号： A01N57/16 , C07F9/09 , C07F9/165 , C07F9/655 , C07D311/70 , A61K31/665 , C07D311/04
CPC分类号： C07F9/65522 , A01N57/16
摘要： Organic phosphoric acid ester derivatives represented by the formula (I): ##STR1## wherein R and R', which may be the same or different, each represents an alkyl group, and A represents a group of atoms necessary to complete together with the two carbon atoms to which they are attached, a 6-membered heterocyclic group containing an oxygen atom as a heteroatom; a process for preparing the same and insecticidal, miticidal or nematocidal compositions containing the same as an active ingredient are disclosed; the compositions exhibit a high ability to control insect pests, mites, nematodes and unhygienic insects harmful to agricultural and horticultural crops.
摘要翻译：由式（I）表示的有机磷酸酯衍生物：其中R和R'可以相同或不同，各自表示烷基，A表示必须一起形成的原子团与它们所连接的两个碳原子一起形成含有氧原子作为杂原子的6元杂环基; 公开了制备与其相同的杀虫剂，杀螨剂或杀线虫剂组合物的方法，该组合物含有作为活性成分的组合物; 该组合物表现出很高的控制对农业和园艺作物有害的害虫，螨虫，线虫和不卫生昆虫的能力。

2. 发明授权

US08409507B2 Automatic analyzer 有权
标题翻译：自动分析仪
公开(公告)号：US08409507B2
公开(公告)日：2013-04-02
申请号：US12056740
申请日：2008-03-27
申请人： Hirokazu Iwamatsu , Kazuhiro Nakamura , Satoshi Shibuya , Yasunao Awata , Hidetoshi Sugiyama , Werner Doppen , Dietmar Kappelhoff
发明人： Hirokazu Iwamatsu , Kazuhiro Nakamura , Satoshi Shibuya , Yasunao Awata , Hidetoshi Sugiyama , Werner Doppen , Dietmar Kappelhoff
IPC分类号： G01N21/00 , G01N31/00 , G01N33/00 , G01N15/06 , G01N33/48
CPC分类号： G01N35/00663 , G01N2035/00673
摘要： An automatic analyzer includes a status table storing the status of each analysis module and reagent information identifying each reagent, the supply of which is exhausted, and allowing tracking of the status of each analysis module, etc. The automatic analyzer determines, based on the status table, whether and how it can continue current analysis, and stores the determination results in its instruction information table. The instruction information table stores analysis-unit or -module operating information and information to be supplied to the user or operator. The analysis-unit operating information includes instructions for the analysis modules to initiate an analysis in a normal manner, finish an analysis in a normal manner, omit a pre-analysis operation, omit a post-analysis operation, or stop sampling, etc. Further, the reagent information and the analysis module status are updated each time a reagent container is replaced by the operator.
摘要翻译：自动分析器包括存储每个分析模块的状态的状态表和识别每个试剂的试剂信息，其供应被耗尽，并且允许跟踪每个分析模块的状态等。自动分析器基于状态表，是否以及如何继续当前分析，并将确定结果存储在其指令信息表中。指令信息表存储要提供给用户或操作者的分析单元或模块操作信息和信息。分析单元操作信息包括分析模块以正常方式启动分析的指令，以正常方式完成分析，省略预分析操作，省略后分析操作或停止采样等。进一步每当试剂容器被操作者代替时，更新试剂信息和分析模块状态。

3. 发明授权

US07750437B2 Semiconductor device having a diode for a rectifier circuit 有权
标题翻译：具有用于整流电路的二极管的半导体器件
公开(公告)号：US07750437B2
公开(公告)日：2010-07-06
申请号：US11229161
申请日：2005-09-19
申请人： Hideaki Suzuki , Hidetoshi Sugiyama
发明人： Hideaki Suzuki , Hidetoshi Sugiyama
IPC分类号： H01L29/93
CPC分类号： H01L27/0814 , H01L21/761 , H01L27/0823
摘要： A semiconductor device has a rectifier circuit and integrated circuit on a semiconductor substrate of a first conduction type, and has a first well region in the substrate, a second well region in first well region, and a diode region formed in second well region and constituting a diode with second well region. The rectifier circuit is formed by the diodes. An input power supply terminal, changing between positive and negative potentials, is connected to second and first well regions of a first diode and to diode region of a second diode. A current supply terminal is provided in the vicinity of first well region of first diode, and is connected to the substrate and a prescribed power supply, so as to supply a current to the PN junction between the first well region and the semiconductor substrate when the input power supply terminal is at negative potential.
摘要翻译：半导体器件在第一导电类型的半导体衬底上具有整流电路和集成电路，并且在衬底中具有第一阱区域，第一阱区域中的第二阱区域和形成在第二阱区域中的二极管区域，并且构成具有第二阱区的二极管。整流电路由二极管形成。在正和负电位之间变化的输入电源端子连接到第一二极管的第二和第一阱区域以及第二二极管的二极管区域。电流源端子设置在第一二极管的第一阱区附近，并且连接到衬底和规定的电源，以便当第一阱区和半导体衬底之间的PN结提供电流时输入电源端子处于负电位。

4. 发明申请

US20120074926A1 INTEGRATED CIRCUIT WITH POWER STATE DETERMINATION CIRCUIT 有权
标题翻译：集成电路与电源状态确定电路
公开(公告)号：US20120074926A1
公开(公告)日：2012-03-29
申请号：US13159543
申请日：2011-06-14
申请人： Hidetoshi Sugiyama , Takayuki Nagasawa , Hideaki Suzuki
发明人： Hidetoshi Sugiyama , Takayuki Nagasawa , Hideaki Suzuki
IPC分类号： G01R19/00
CPC分类号： H01L27/0274 , G01R31/026 , G01R31/2884
摘要： An integrated circuit in which a power terminal, a ground terminal, an input terminal and an internal circuit are formed, has a unidirectional circuit of a direction from the input terminal to the power terminal, the unidirectional circuit being provided between the input terminal and the power terminal; and a power state determination circuit which detects whether the power terminal is connected to an external power source or not to output a power open detection signal. And the unidirectional circuit includes a first transistor in which a voltage of the power terminal is applied to a gate, and a second transistor connected to the first transistor in series, and a voltage of the external power source is input to the input terminal.
摘要翻译：形成有电源端子，接地端子，输入端子和内部电路的集成电路具有从输入端子到电源端子的方向的单向电路，单向电路设置在输入端子和电源端子; 以及电源状态确定电路，其检测电源端子是否连接到外部电源以输出电源打开检测信号。单向电路包括：第一晶体管，其中电源端子的电压施加到栅极;以及第二晶体管，其串联连接到第一晶体管，并且外部电源的电压被输入到输入端子。

5. 发明申请

US20070203662A1 Testing circuit and testing method for semiconductor device and semiconductor chip 有权
标题翻译：半导体器件和半导体芯片的测试电路和测试方法
公开(公告)号：US20070203662A1
公开(公告)日：2007-08-30
申请号：US11474393
申请日：2006-06-26
申请人： Hidetoshi Sugiyama , Masao Nakajima , Haruyuki Mouri , Hideaki Suzuki
发明人： Hidetoshi Sugiyama , Masao Nakajima , Haruyuki Mouri , Hideaki Suzuki
IPC分类号： G06F19/00
CPC分类号： G01R31/31719 , G01R31/31701 , G01R31/31721
摘要： A testing circuit for a semiconductor device having a test mode in which the information about built-in memory cannot be read after conducting a test on a semiconductor device, and cutting a pad formed in a scribe area is provided. The scribe PAD and the scribe ROM are formed in the cutting area of a wafer. Upon power-up of a chip a, the power-on reset circuit transmits a reset signal to the mode register. After setting the initial resister value to “00”, a mode switch signal is input from the mode switch terminal, the scribe ROM is activated, and the test mode is set. In this process, a Manchester coded signal is provided from the scribe PAD, decoded by a clock of dividing frequency provided from the clock dividing circuit, the value of the register in the test mode in the mode register is set, and external reset is asserted or negated.
摘要翻译：一种半导体器件的测试电路，具有测试模式，其中在对半导体器件进行测试之后无法读取关于内置存储器的信息，并且切割形成在划线区域中的焊盘。划片PAD和划线ROM形成在晶片的切割区域中。在芯片a上电时，上电复位电路将复位信号发送到模式寄存器。将初始电阻值设置为“00”后，从模式开关端子输入模式切换信号，激活划线ROM，并设置测试模式。在这个过程中，曼彻斯特编码信号由划片PAD提供，由时钟分频电路提供的分频时钟解码，设置模式寄存器中的测试模式中的寄存器的值，并且断言外部复位或否定。

6. 发明申请

US20060273403A1 Semiconductor device having a diode for a rectifier circuit 有权
标题翻译：具有用于整流电路的二极管的半导体器件
公开(公告)号：US20060273403A1
公开(公告)日：2006-12-07
申请号：US11229161
申请日：2005-09-19
申请人： Hideaki Suzuki , Hidetoshi Sugiyama
发明人： Hideaki Suzuki , Hidetoshi Sugiyama
IPC分类号： H01L29/76
CPC分类号： H01L27/0814 , H01L21/761 , H01L27/0823
摘要： A semiconductor device has a rectifier circuit and integrated circuit on a semiconductor substrate of a first conduction type, and has a first well region in the substrate, a second well region in first well region, and a diode region formed in second well region and constituting a diode with second well region. The rectifier circuit is formed by the diodes. An input power supply terminal, changing between positive and negative potentials, is connected to second and first well regions of a first diode and to diode region of a second diode. A current supply terminal is provided in the vicinity of first well region of first diode, and is connected to the substrate and a prescribed power supply, so as to supply a current to the PN junction between the first well region and the semiconductor substrate when the input power supply terminal is at negative potential.
摘要翻译：半导体器件在第一导电类型的半导体衬底上具有整流电路和集成电路，并且在衬底中具有第一阱区域，第一阱区域中的第二阱区域和形成在第二阱区域中的二极管区域，并且构成具有第二阱区的二极管。整流电路由二极管形成。在正和负电位之间变化的输入电源端子连接到第一二极管的第二和第一阱区域以及第二二极管的二极管区域。电流源端子设置在第一二极管的第一阱区附近，并且连接到衬底和规定的电源，以便当第一阱区和半导体衬底之间的PN结提供电流时输入电源端子处于负电位。

7. 发明授权

US08765474B2 Automatic analyzer and the analyzing method using the same 有权
标题翻译：自动分析仪及其分析方法
公开(公告)号：US08765474B2
公开(公告)日：2014-07-01
申请号：US12032339
申请日：2008-02-15
申请人： Katsuhiro Kambara , Shigenori Watari , Hidetoshi Sugiyama
发明人： Katsuhiro Kambara , Shigenori Watari , Hidetoshi Sugiyama
IPC分类号： G01N35/02
CPC分类号： G01N35/1002 , G01N35/1016 , G01N2035/00465 , G01N2035/00891 , G01N2035/1058
摘要： An automatic analyzer which assures uniformity in mixing effects regardless of sample quantity and test item and thus produces analysis results with high repeatability. The automatic analyzer includes a device for adding a conditioning liquid into a reaction chamber so that the quantity of liquid in the reaction chamber becomes a predetermined quantity prior to being mixed. The conditioning liquid may be a diluent or physiological saline as used for dilution of a sample or any other special liquid that adjusts the properties such as viscosity, surface tension, etc. of liquid to be mixed.
摘要翻译：一种自动分析仪，无论样品数量和检测项目如何，都能确保混合效果的均匀性，从而产生高重复性的分析结果。自动分析装置包括用于将调节液体添加到反应室中的装置，使得在混合之前反应室中的液体量变为预定量。调理液体可以是用于稀释样品或任何其它特殊液体的稀释剂或生理盐水，其调节待混合的液体的粘度，表面张力等性质。

8. 发明授权

US08754632B2 Integrated circuit with power state determination circuit 有权
标题翻译：具有电源状态确定电路的集成电路
公开(公告)号：US08754632B2
公开(公告)日：2014-06-17
申请号：US13159543
申请日：2011-06-14
申请人： Hidetoshi Sugiyama , Takayuki Nagasawa , Hideaki Suzuki
发明人： Hidetoshi Sugiyama , Takayuki Nagasawa , Hideaki Suzuki
IPC分类号： G01R19/00
CPC分类号： H01L27/0274 , G01R31/026 , G01R31/2884
摘要： An integrated circuit in which a power terminal, a ground terminal, an input terminal and an internal circuit are formed, has a unidirectional circuit of a direction from the input terminal to the power terminal, the unidirectional circuit being provided between the input terminal and the power terminal; and a power state determination circuit which detects whether the power terminal is connected to an external power source or not to output a power open detection signal. And the unidirectional circuit includes a first transistor in which a voltage of the power terminal is applied to a gate, and a second transistor connected to the first transistor in series, and a voltage of the external power source is input to the input terminal.
摘要翻译：形成有电源端子，接地端子，输入端子和内部电路的集成电路具有从输入端子到电源端子的方向的单向电路，单向电路设置在输入端子和电源端子; 以及电源状态确定电路，其检测电源端子是否连接到外部电源以输出电源打开检测信号。单向电路包括：第一晶体管，其中电源端子的电压施加到栅极;以及第二晶体管，其串联连接到第一晶体管，并且外部电源的电压被输入到输入端子。

9. 发明授权

US07603248B2 Testing circuit and testing method for semiconductor device and semiconductor chip 有权
标题翻译：半导体器件和半导体芯片的测试电路和测试方法
公开(公告)号：US07603248B2
公开(公告)日：2009-10-13
申请号：US11474393
申请日：2006-06-26
申请人： Hidetoshi Sugiyama , Masao Nakajima , Haruyuki Mouri , Hideaki Suzuki
发明人： Hidetoshi Sugiyama , Masao Nakajima , Haruyuki Mouri , Hideaki Suzuki
IPC分类号： G06F19/00
CPC分类号： G01R31/31719 , G01R31/31701 , G01R31/31721
摘要： A testing circuit for a semiconductor device having a test mode in which the information about built-in memory cannot be read after conducting a test on a semiconductor device, and cutting a pad formed in a scribe area is provided. The scribe PAD and the scribe ROM are formed in the cutting area of a wafer. Upon power-up of a chip a, the power-on reset circuit transmits a reset signal to the mode register. After setting the initial resister value to “00”, a mode switch signal is input from the mode switch terminal, the scribe ROM is activated, and the test mode is set. In this process, a Manchester coded signal is provided from the scribe PAD, decoded by a clock of dividing frequency provided from the clock dividing circuit, the value of the register in the test mode in the mode register is set, and external reset is asserted or negated.
摘要翻译：一种半导体器件的测试电路，具有测试模式，其中在对半导体器件进行测试之后无法读取关于内置存储器的信息，并且切割形成在划线区域中的焊盘。划片PAD和划线ROM形成在晶片的切割区域中。在芯片a上电时，上电复位电路将复位信号发送到模式寄存器。将初始电阻值设置为“00”后，从模式开关端子输入模式切换信号，激活划线ROM，并设置测试模式。在这个过程中，曼彻斯特编码信号由划片PAD提供，由时钟分频电路提供的分频时钟解码，设置模式寄存器中的测试模式中的寄存器的值，并且断言外部复位或否定。

10. 发明授权

US07360984B1 Automatic analyzer and part feeding device used for the analyzer 有权
标题翻译：用于分析仪的自动分析仪和零件进料装置
公开(公告)号：US07360984B1
公开(公告)日：2008-04-22
申请号：US10069580
申请日：2000-03-15
申请人： Hidetoshi Sugiyama , Katsuaki Takahashi , Hideyuki Yanami , Stephan Sattler
发明人： Hidetoshi Sugiyama , Katsuaki Takahashi , Hideyuki Yanami , Stephan Sattler
IPC分类号： B65G59/08
CPC分类号： B01L9/543 , G01N35/028 , G01N35/04 , G01N2035/0425 , G01N2035/0427 , G01N2035/103
摘要： An automatic analyzer, comprising disposable parts such as large quantities of nozzle tips and reaction containers for use in sample analysis inspection, wherein the part rack (12) holding unused parts is raised from a lowest position to a rack separation station (A) by a lift for supply (14) and separated so that only the uppermost stacked part rack can remain on the rack separation station, the separated part rack is moved to a part take-out station (B) where parts on the part rack are taken out one by one from a movable holding part (59), and, by opening the floor part of the part take-out station (B) after part consumption, the used part rack is allowed to fall down and recovered on the lift (84) of a recovery lifter (15), whereby the supply of an unused part rack on which unused parts are loaded and the recovery of a used part rack can be performed with a compact system configuration.
摘要翻译：一种自动分析仪，其包括一次性部件，例如用于样品分析检查的大量喷嘴尖端和反应容器，其中保持未使用部分的部件齿条（12）从最低位置升高到齿条分离站（A），由电梯供应（14）并分离，使得只有最上层堆叠的机架可以保留在机架分离站上，分离的机架架移动到零件取出站（B），在零件取出站（B）取出零件机架上的零件1 通过一个来自可移动的保持部分（59），并且通过在零件消耗之后打开部件取出站（B）的地板部分，允许使用的部件架在电梯（84）的升降机（84）上落下并回收回收提升器（15），其中可以以紧凑的系统配置来执行其上装载有未使用部件的未使用部件机架的供应和使用的部件机架的恢复。

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