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1. 发明授权

US5130671A Phase-locked loop frequency tracking device including a direct digital synthesizer 失效
标题翻译：包括直接数字合成器的锁相环路跟踪装置
公开(公告)号：US5130671A
公开(公告)日：1992-07-14
申请号：US633864
申请日：1990-12-26
申请人： Iradj Shahriary , Kevin M. McNab
发明人： Iradj Shahriary , Kevin M. McNab
IPC分类号： H03L7/08 , H03L7/099 , H03L7/10 , H03L7/12
CPC分类号： H03L7/0994 , H03L7/10 , H03L7/12
摘要： Disclosed is a single phase-locked loop (50, 350) providing tuning over a very large bandwidth for use in wide band carrier tracking and clock recovery systems. In a first embodiment, a DC signal is formed representative of a phase difference between an input signal changing with time and a return signal. The DC signal is applied to a narrow band voltage controlled oscillator (68) which converts the DC signal back to an AC signal. The AC signal is level shifted to form a clocking pulse for an accumulator (80) of a direct digital synthesizer (72). A digital command word is also applied to the accumulator (80), such that the digital command word represents a coarse tuning of the input frequency. The clocking pulse from the narrow band VCO (68) supplies a fine tuning of the input frequency. In a second embodiment, the DC representative phase signal is applied to an analog-to-digital converter (364) which produces an N-bit word representative of the phase difference. The change in phase alters the digital output of the analog-to-digital converter (364) which in turn is applied to the accumulator (376) of a direct digital synthesizer (370). By this invention, very wide band tracting is capable with a single phase-locked loop, thus limiting the hardware and cost.

2. 发明授权

US4918748A Apparatus and method for phase noise and post tuning drift cancellation 失效
标题翻译：相位噪声和后调谐漂移消除的装置和方法
公开(公告)号：US4918748A
公开(公告)日：1990-04-17
申请号：US118902
申请日：1987-11-09
申请人： Iradj Shahriary , Kevin M. McNab
发明人： Iradj Shahriary , Kevin M. McNab
IPC分类号： H04B1/26 , H03B21/02 , H03D7/16 , H03L7/20 , H04B1/10
CPC分类号： H03D7/163 , H03L7/20 , H03B21/02
摘要： The tuner section of a communications receiver 10 includes a gallium arsenide voltage controlled oscillator 48 for upconverting the received signal in mixer 18. Phase noise and post tuning drift associated with oscillator 48 is impressed onto the signal supplied by a second oscillator network 46. Thus, the outputs of mixers 18 and 78 both contain noise and post tuning drift associated with the gallium arsenide oscillator 48. Mixer 28 is used to substract the noise and drift component on line 30 from that on line 32 to thereby provide an output 14 which is substantially free of the noise and drift associated with the efficient, but noisy gallium arsenide VCO 48.

3. 发明授权

US5184092A Phase-locked loop frequency tracking device including a direct digital synthesizer 失效
标题翻译：锁相环频率跟踪装置包括直接数字合成器
公开(公告)号：US5184092A
公开(公告)日：1993-02-02
申请号：US899391
申请日：1992-06-16
申请人： Iradj Shahriary , Kevin M. McNab
发明人： Iradj Shahriary , Kevin M. McNab
IPC分类号： H03L7/099 , H03L7/10 , H03L7/12
CPC分类号： H03L7/0994 , H03L7/10 , H03L7/12
摘要： Disclosed is a single phase-locked loop (50, 350) providing tuning over a very large bandwidth for use in wide band carrier tracking and clock recovery systems. In a first embodiment, a DC signal is formed representative of a phase difference between an input signal changing with time and a return signal. The DC signal is applied to a narrow band voltage controlled oscillator (68) which converts the DC signal back to an AC signal. The AC signal is level shifted to form a clocking pulse for an accumulator (80) of a direct digital synthesizer (72). A digital command word is also applied to tyhe accumulator (80), such that the digital command word represents a coarse tuning of the input frequency. The clocking pulse from the narrow band VCO (68) supplies a fine tuning of the input frequency.
摘要翻译：公开了单个锁相环（50,350），其提供在非常大的带宽上的调谐以用于宽带载波跟踪和时钟恢复系统。在第一实施例中，形成DC信号，代表输入信号随时间变化和返回信号之间的相位差。 DC信号被施加到窄带压控振荡器（68），其将DC信号转换回AC信号。 AC信号被电平移位以形成用于直接数字合成器（72）的累加器（80）的时钟脉冲。数字命令字也被应用于累加器（80），使得数字命令字表示输入频率的粗调。来自窄带VCO（68）的时钟脉冲提供输入频率的微调。

4. 发明授权

US5019793A Digitally implemented variable phase shifter and amplitude weighting device 失效
标题翻译：数字实现可变移相器和幅度加权装置
公开(公告)号：US5019793A
公开(公告)日：1991-05-28
申请号：US526160
申请日：1990-05-21
申请人： Kevin M. McNab
发明人： Kevin M. McNab
IPC分类号： H01P5/04
CPC分类号： H01P5/04
摘要： A variable phase shifter and amplitude weighting (VPSAW) device capable of selectively varying the phase and amplitude of an incoming RF signal (RF.sub.IN) in such a manner as to produce an output RF signal (RF.sub.OUT) having a selected phase and amplitude, by means of splitting the RF.sub.IN signal into first and second signal components, selectively shifting the phase of each of these two components, and then combining the thusly selectively phase-shifted first and second signal components. In the presently contemplated best mode of the present invention, the VPSAW device includes digitally-implemented componentry, e.g., microprocessor-controlled direct, digital synthesizers, for generating first and second control signals, e.g., selectively phase-shifted sinusoidal signals, indicative of first and second phase shift increments, .phi..sub.a and .phi..sub.b, respectively, to be imparted to the first and second signal components, respectively. The VPSAW device of the best mode further includes first and second signal mixers for mixing together the first and second control signals with the corresponding first and second signal components, to thereby phase shift the first and second signal components by the first and second phase increments .phi..sub.a and .phi..sub. b, respectively. The first and second phase shift increments, .phi..sub.a and .phi..sub.b, satisfy a prescribed algorithm which results in the RF.sub.OUT signal having the selected phase (.phi..sub.c) and the selected amplitude (C), e.g., .phi..sub.a =.phi..sub.c +COS.sup.-1 (1/2 C) and .phi..sub.b =.phi..sub.c -COS.sup.-1 (1/2 C). Additionally, the first and second mixers may serve to downconvert the RF.sub.IN signal by subtracting the frequency of the first and second control signals from the frequency of the first and second signal components.
摘要翻译：一种可变移相器和幅度加权（VPSAW）装置，其能够以这样的方式选择性地改变输入RF信号（RFIN）的相位和幅度，以便通过装置产生具有所选相位和幅度的输出RF信号（RFOUT）将RFIN信号分解成第一和第二信号分量，选择性地移位这两个分量中的每一个的相位，然后组合由此选择性地相移的第一和第二信号分量。在本发明的目前设想的最佳模式中，VPSAW设备包括数字实现的组件，例如微处理器控制的直接数字合成器，用于产生第一和第二控制信号，例如，选择性地相移正弦信号，和分别赋予第一和第二信号分量的第二相移增量，phi和phi b。最佳模式的VPSAW设备还包括用于将第一和第二控制信号与对应的第一和第二信号分量混合在一起的第一和第二信号混合器，从而将第一和第二信号分量相移第一和第二相位增量phi a和phi b。第一和第二相移增量（phi a和phi b）满足规定的算法，其导致RFOUT信号具有所选择的相位（phi）和所选择的幅度（C），例如，phi a = phi c + COS- 1（1/2 C）和phi b = phi-COS-1（1/2 C）。此外，第一和第二混频器可以用于通过从第一和第二信号分量的频率减去第一和第二控制信号的频率来对RFIN信号进行下变频。

5. 发明授权

US5014231A Randomized digital/analog converter direct digital synthesizer 失效
标题翻译：随机数字/模拟转换器直接数字合成器
公开(公告)号：US5014231A
公开(公告)日：1991-05-07
申请号：US380786
申请日：1989-07-17
申请人： Victor S. Reinhardt , Kim V. Gould , Kevin M. McNab
发明人： Victor S. Reinhardt , Kim V. Gould , Kevin M. McNab
IPC分类号： G06F1/03
CPC分类号： G06F1/0328 , G06F2211/902
摘要： A sine output or phase interpolation direct digital synthesizer for use in satellite programs having a random or pseudorandom code generator for summing a random digital word whose value ranges from zero to just under the least significant bit of a digital-to-analog converter with the current register value normally sent to the converter for reducing the spurious sidebands associated with the finite resolution of the converter within the synthesizer, the sum being truncated to the resolution of the converter and for controlling the converter, the spurious sidebands being reduced by randomization of the periodic behavior associated with the truncation process while lowering the total phase noise.
摘要翻译：正弦输出或相位插值直接数字合成器，用于具有随机或伪随机码发生器的卫星程序中，用于将数值范围从零到刚好在具有当前数字 - 模拟转换器的最低有效位之间的随机数字字通常发送到转换器的寄存器值用于减少与合成器内的转换器的有限分辨率相关联的寄生边带，该和被截断到转换器的分辨率并用于控制转换器，通过周期性的随机化来减少杂散边带降低总相位噪声时与截断过程相关的行为。

6. 发明授权

US6075701A Electronic structure having an embedded pyrolytic graphite heat sink material 有权
标题翻译：具有嵌入式热解石墨散热材料的电子结构
公开(公告)号：US6075701A
公开(公告)日：2000-06-13
申请号：US312460
申请日：1999-05-14
申请人： M. Akbar Ali , Carl W. Peterson , Kevin M. McNab
发明人： M. Akbar Ali , Carl W. Peterson , Kevin M. McNab
IPC分类号： H01L23/373 , H05K7/20
CPC分类号： H01L23/3732 , H01L2924/0002 , H01L2924/3011 , Y10T428/12486 , Y10T428/12625
摘要： An electronic structure includes an electronic device, and a heat sink assembly in thermal contact with the electronic device. The heat sink assembly is formed of a piece of pyrolytic graphite embedded within a metallic casing and intimately contacting an interior wall of the metallic casing. The heat sink assembly is substantially fully dense. The heat sink assembly is fabricated by assembling the piece of pyrolytic graphite within the disassembled elements of the metallic casing, and then simultaneously heating and pressing the initial assembly until it is substantially fully dense.
摘要翻译：电子结构包括电子设备和与电子设备热接触的散热器组件。散热器组件由嵌入金属壳体内的热解石墨片形成，并与金属外壳的内壁紧密接触。散热器组件基本上是完全致密的。散热器组件通过将金属壳体的分解元件中的热解石墨块组装在一起而制成，然后同时加热和压制初始组件，直到其基本上完全致密。

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