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1. 发明授权

US6097326A Algorithmic analog-to-digital converter with reduced differential non-linearity and method 失效
标题翻译：具有降低差分非线性和方法的算法模数转换器
公开(公告)号：US6097326A
公开(公告)日：2000-08-01
申请号：US84543
申请日：1998-05-26
申请人： Ion E. Opris , Sing W. Chin , Bill C. Wong , Satoshi Sakurai
发明人： Ion E. Opris , Sing W. Chin , Bill C. Wong , Satoshi Sakurai
IPC分类号： H03M1/06 , H03M1/44 , H03M1/38
CPC分类号： H03M1/442 , H03M1/0612
摘要： An analog to digital converter section for use in an analog to digital converter which includes a converter stage which produces a digital and an residue output. The residue output is applied to an over-range stage which produces a second residue output equal to the first residue output reduced in magnitude by the magnitude of a reference voltage. The over-range stage is capable of operating with a relatively high feedback factor to increase operating speed and with commutated feedback-capacitor switching to reduce differential non-linearity errors.
摘要翻译：一种用于模数转换器的模数转换器部分，其包括产生数字和残留输出的转换器级。剩余输出被施加到超范围级，其产生等于第一残余输出的第二残余输出，其大小减小参考电压的幅度。超范围级能够以相对较高的反馈因子运行，以提高运行速度，并具有换向反馈电容器切换以减少差分非线性误差。

2. 发明授权

US5889486A Split capacitor array for digital-to-analog signal conversion 失效
标题翻译：分离电容阵列用于数模转换
公开(公告)号：US5889486A
公开(公告)日：1999-03-30
申请号：US933233
申请日：1997-09-18
申请人： Ion E. Opris , Bill C. Wong
发明人： Ion E. Opris , Bill C. Wong
IPC分类号： H03M1/46 , H03M1/68 , H03M1/66
CPC分类号： H03M1/68 , H03M1/468
摘要： A capacitor array-based, successive approximation analog-to-digital signal converter includes a capacitor array with a central coupling capacitor having a unit-value capacitance and two sets of input coupling capacitors having capacitances which are binary weighted multiples of such unit-value capacitance. During the sampling phase, the first set of input coupling capacitors is grounded while the second set of input coupling capacitors is driven by the analog input voltage. During the holding, or conversion, phase, one of the input coupling capacitors in the second set is grounded while each one of the input coupling capacitors in the first set and each one of the remaining input coupling capacitors in the second set is driven by a respective binary multiple of a fixed reference voltage, with each one of such binary multiples corresponding to one of the bits of the successive approximation result.
摘要翻译：基于电容器阵列的逐次逼近模数 - 信号转换器包括具有单位值电容的中心耦合电容器的电容器阵列和具有作为这种单位电容的二进制加权倍数的电容的两组输入耦合电容器。在采样阶段，第一组输入耦合电容接地，第二组输入耦合电容由模拟输入电压驱动。在保持或转换相位期间，第二组中的输入耦合电容器之一接地，而第一组中的每一个输入耦合电容器和第二组中的每个剩余的输入耦合电容器被驱动固定参考电压的相应二进制倍数，其中这些二进制倍数中的每一个对应于逐次逼近结果的比特之一。

3. 发明授权

US07187318B1 Pipeline ADC using multiplying DAC and analog delay circuits 有权
标题翻译：管道ADC采用倍增DAC和模拟延迟电路
公开(公告)号：US07187318B1
公开(公告)日：2007-03-06
申请号：US11198970
申请日：2005-08-08
申请人： Bumha Lee , Sing W. Chin , Bill C. Wong
发明人： Bumha Lee , Sing W. Chin , Bill C. Wong
IPC分类号： H03M1/38
CPC分类号： H03M1/168
摘要： Each stage of a pipeline ADC includes an analog delay cell, a sub-stage ADC, and a multiplying digital-to-analog converter (MDAC). The MDAC includes a sample-and-hold amplifier (SHA) circuit, a summer, a gain stage, and a DAC. The MDAC is arranged in cooperation with the analog delay cell such that the effects of a long comparator decision time under high-speed conditions are minimized. The first SHA, half clock cycle delay cell with unity gain transfer function, samples the input signal during the first clock period, followed by a strobe of the sub-ADC. Substantially half of the clock period can be utilized for the comparison time of the sub-ADC using the described methods. Since decoding is completed before MDAC sampling the first SHA output so that the complete half clock cycle can be arranged for amplifier settling in order to achieve the maximum operating speed with a given amplifier bandwidth.
摘要翻译：流水线ADC的每个级包括模拟延迟单元，子级ADC和乘法数模转换器（MDAC）。 MDAC包括采样保持放大器（SHA）电路，加法器，增益级和DAC。 MDAC与模拟延迟单元配合配置，使得在高速条件下的长比较器判定时间的影响最小化。第一个具有单位增益传递函数的SHA半时钟周期延迟单元，在第一个时钟周期内采样输入信号，随后是子ADC的选通。基本上一半的时钟周期可以用于使用所述方法的子ADC的比较时间。由于在MDAC对第一个SHA输出进行采样之前完成了解码，所以可以将完整的半个时钟周期安排用于放大器稳定，以便在给定的放大器带宽下实现最大工作速度。

4. 发明授权

US07705649B1 Duty cycle correction circuit with small duty error and wide frequency range 有权
标题翻译：占空比校正电路，占空比小，频率范围宽
公开(公告)号：US07705649B1
公开(公告)日：2010-04-27
申请号：US12062426
申请日：2008-04-03
申请人： Hao Yu , Sing W. Chin , Bill C. Wong
发明人： Hao Yu , Sing W. Chin , Bill C. Wong
IPC分类号： H03K3/017
CPC分类号： H03K5/1565 , H03K2005/00097 , H03K2005/00208 , H03L7/0812 , H03L7/0891 , H03L7/093
摘要： A duty cycle correction circuit (10) for receiving an input clock signal (11) and generating an output clock signal (13) having a predetermined duty cycle includes a clock trigger circuit (12) generating the output clock signal (13) having a first clock edge triggered from the input clock signal and a second clock edge triggered from a delayed clock signal (22); a charge pump circuit (14) receiving the output clock signal and generating charging and discharging currents for a capacitor (C1) where a control voltage develops on the capacitor indicative of the duty cycle error of the output clock signal; a self-track bias circuit (18) receiving the control voltage and generating first and second bias voltages (23, 24) in response to the control voltage; and a delay-locked loop circuit (20) receiving the output clock signal and the first and second bias voltages and generating the delayed clock signal.
摘要翻译：一种用于接收输入时钟信号（11）并产生具有预定占空比的输出时钟信号（13）的占空比校正电路（10）包括：时钟触发电路（12），产生具有第一从所述输入时钟信号触发时钟沿和从延迟的时钟信号（22）触发的第二时钟沿; 电荷泵电路（14），接收所述输出时钟信号，并且产生电容器（C1）的充电和放电电流，其中在所述电容器上产生控制电压，其指示所述输出时钟信号的占空比误差; 接收所述控制电压并且响应于所述控制电压产生第一和第二偏置电压（23,24）的自磁道偏置电路（18）; 以及延迟锁定环路（20），接收所述输出时钟信号和所述第一和第二偏置电压并产生延迟的时钟信号。

5. 发明授权

US5638071A Efficient architecture for correcting component mismatches and circuit nonlinearities in A/D converters 失效
标题翻译：用于校正A / D转换器中元件失配和电路非线性的高效架构
公开(公告)号：US5638071A
公开(公告)日：1997-06-10
申请号：US662273
申请日：1996-06-12
申请人： Peter D. Capofreddi , Edison Fong , Bill C. Wong
发明人： Peter D. Capofreddi , Edison Fong , Bill C. Wong
IPC分类号： H03M1/10 , H03M1/12 , H03M1/06
CPC分类号： H03M1/1047 , H03M1/12
摘要： An error correction technique for high-resolution analog-to-digital converters corrects for both component mismatch and circuit nonlinearity errors by utilizing look-up tables to store mismatch coefficients, which represent the errors introduced by component mismatch, as well as a series of offset and gain coefficients, which are utilized to form a piecewise-linear representation of the error introduced by circuit nonlinearities. The use of an independent gain and offset parameter for each segment of the piecewise-linear representation allows discontinuous functions to be accommodated. This leads to a more efficient implementation since it allows the error introduced by mismatch in the components representing the most significant bits to be included in the piecewise linear table, while separate lookup tables are used for the less significant bits.
摘要翻译：用于高分辨率模数转换器的纠错技术通过利用查找表来存储失配系数来校正元件失配和电路非线性误差，这些失真系数表示由元件失配引入的误差以及一系列偏移和增益系数，用于形成由电路非线性引入的误差的分段线性表示。对分段线性表示的每个段使用独立的增益和偏移参数允许适应不连续的功能。这导致更有效的实现，因为它允许由表示最高有效位的组件中的不匹配引入的错误被包括在分段线性表中，而单独的查找表用于较低有效位。

6. 发明授权

US5416369A High-sensitivity high-resolution comparator 失效
标题翻译：高灵敏度高分辨率比较器
公开(公告)号：US5416369A
公开(公告)日：1995-05-16
申请号：US115886
申请日：1993-09-01
申请人： Edison Fong , Bill C. Wong
发明人： Edison Fong , Bill C. Wong
IPC分类号： G01R19/165 , G01R19/00 , H03K5/08 , H03M1/34 , H03K5/24
CPC分类号： G01R19/0038
摘要： The comparison circuitry of a comparator is isolated from noise on the power supply and ground by utilizing transistors operating in the forward-active region to isolate the comparison circuitry. The comparison circuitry is further isolated from random noise spikes by utilizing delay and switching circuitry to control the duration of the comparison.
摘要翻译：比较器的比较电路通过利用在正向有源区中工作的晶体管来隔离比较电路而与电源和地之间的噪声隔离。通过利用延迟和切换电路来控制比较的持续时间，比较电路进一步与随机噪声尖峰隔离。

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