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1. 发明申请

US20160321662A1 CUSTOMER LOAD OF FIELD PROGRAMMABLE GATE ARRAYS 有权
标题翻译：现场可编程门阵列的客户负载
公开(公告)号：US20160321662A1
公开(公告)日：2016-11-03
申请号：US14698117
申请日：2015-04-28
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Todd W. Arnold , Mark A. Check , Vincenzo Condorelli
IPC分类号： G06Q20/40 , H04L9/08
CPC分类号： G06F21/62 , G06F21/6209 , G06F21/76 , G06Q20/341 , G06Q20/3552 , G06Q2220/00 , G09C1/00 , H04L9/0822 , H04L9/0877 , H04L9/14 , H04L2209/24
摘要： Customer content is securely loaded on a field programmable gate array (FPGA) located on a secure cryptography card. The customer content is loaded such that it may not be extracted. A customer obtains a secure cryptography card that includes a field programmable gate array and a master key generated by the secure cryptography card. The customer loads customer specific content on the field programmable gate array, wherein, based on the loading, the customer specific content is secure from extraction via the master key by at least entities other than the customer.
摘要翻译：客户内容安全地加载在位于安全加密卡上的现场可编程门阵列（FPGA）上。加载客户内容使其不会被提取。客户获得包括现场可编程门阵列和由安全加密卡产生的主密钥的安全加密卡。客户在现场可编程门阵列上加载客户特定的内容，其中，基于加载，客户特定的内容通过至少除客户之外的实体的主密钥从主密钥提取是安全的。

2. 发明申请

US20160147687A1 ARBITRATION IN AN SRIOV ENVIRONMENT 审中-公开
公开(公告)号：US20160147687A1
公开(公告)日：2016-05-26
申请号：US14552666
申请日：2014-11-25
申请人： International Business Machines Corporation
发明人： Mark A. Check , Vincenzo Condorelli , Nihad Hadzic , William Santiago Fernandez
IPC分类号： G06F13/372 , G06F13/42 , G06F1/24 , G06F9/455
CPC分类号： G06F13/3625 , G06F1/24 , G06F9/45558 , G06F13/372 , G06F13/4221 , G06F2009/45579
摘要： In one embodiment, a computer-implemented method includes assigning a time budget to each of a plurality of virtual functions in a single-root input/output (SRIOV) environment, where a first time budget of a first virtual function indicates a quantity of cycles on an engine of the SRIOV environment allowed to the first virtual function within a time slice. A plurality of requests issued by the plurality of virtual functions are selected by a computer processor, where the selecting excludes requests issued by virtual functions that have used their associated time budgets of cycles in a current time slice. The selected plurality of requests are delivered to the engine for processing. The time budgets of the virtual functions are reset and a new time slice begins, at the end of the current time slice.

3. 发明申请

US20160147685A1 ARBITRATION IN AN SRIOV ENVIRONMENT 审中-公开
标题翻译： SRIOV环境中的仲裁
公开(公告)号：US20160147685A1
公开(公告)日：2016-05-26
申请号：US14844053
申请日：2015-09-03
申请人： International Business Machines Corporation
发明人： Mark A. Check , Vincenzo Condorelli , Nihad Hadzic , William Santiago Fernandez
IPC分类号： G06F13/362 , G06F9/455
CPC分类号： G06F13/3625 , G06F1/24 , G06F9/45558 , G06F13/372 , G06F13/4221 , G06F2009/45579
摘要： In one embodiment, a computer-implemented method includes assigning a time budget to each of a plurality of virtual functions in a single-root input/output (SRIOV) environment, where a first time budget of a first virtual function indicates a quantity of cycles on an engine of the SRIOV environment allowed to the first virtual function within a time slice. A plurality of requests issued by the plurality of virtual functions are selected by a computer processor, where the selecting excludes requests issued by virtual functions that have used their associated time budgets of cycles in a current time slice. The selected plurality of requests are delivered to the engine for processing. The time budgets of the virtual functions are reset and a new time slice begins, at the end of the current time slice.
摘要翻译：在一个实施例中，计算机实现的方法包括在单根输入/输出（SRIOV）环境中为多个虚拟功能中的每一个分配时间预算，其中第一虚拟功能的第一时间预算指示周期数在SRIOV环境的引擎上允许在时间片内的第一个虚拟功能。由计算机处理器选择由多个虚拟功能发出的多个请求，其中选择不包括在当前时间片中已经使用其相关联的周期时间预算的虚拟功能发出的请求。所选择的多个请求被传送到引擎进行处理。在当前时间片的末尾，虚拟功能的时间预算被重置并且新的时间片开始。

4. 发明申请

US20140115405A1 INTEGRITY CHECKING INCLUDING SIDE CHANNEL MONITORING 有权
标题翻译：完整性检查，包括侧面通道监测
公开(公告)号：US20140115405A1
公开(公告)日：2014-04-24
申请号：US13659207
申请日：2012-10-24
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Vincenzo Condorelli , Silvio Dragone , Tamas Visegrady
IPC分类号： G06F11/07
CPC分类号： G06F21/556 , G06F21/577 , G06F2221/2125
摘要： A method for integrity checking for a cryptographic engine in a computing system includes monitoring a state of a side channel of the cryptographic engine during operation of the cryptographic engine by a side channel monitor; comparing the state of the side channel to a side channel model of the cryptographic engine to determine whether a mismatch exists between the state of the side channel and the side channel model; and based on a mismatch between the state of the side channel and the model of the side channel, indicating an error in the cryptographic engine.
摘要翻译：一种用于计算系统中的加密引擎的完整性检查的方法，包括：在侧信道监视器的操作期间监视加密引擎的侧信道的状态; 将侧信道的状态与密码引擎的侧信道模型进行比较，以确定侧信道的状态与侧信道模型之间是否存在不匹配; 并且基于侧信道的状态与侧信道的模型之间的不匹配，指示密码引擎中的错误。

5. 发明申请

US20170161510A1 CUSTOMER LOAD OF FIELD PROGRAMMABLE GATE ARRAYS 有权
公开(公告)号：US20170161510A1
公开(公告)日：2017-06-08
申请号：US15440631
申请日：2017-02-23
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Todd W. Arnold , Mark A. Check , Vincenzo Condorelli
IPC分类号： G06F21/62 , H04L9/08 , H04L9/14 , G09C1/00
CPC分类号： G06F21/62 , G06F21/6209 , G06F21/76 , G06Q20/341 , G06Q20/3552 , G06Q2220/00 , G09C1/00 , H04L9/0822 , H04L9/0877 , H04L9/14 , H04L2209/24
摘要： Customer content is securely loaded on a field programmable gate array (FPGA) located on a secure cryptography card. The customer content is loaded such that it may not be extracted. A customer obtains a secure cryptography card that includes a field programmable gate array and a master key generated by the secure cryptography card. The customer loads customer specific content on the field programmable gate array, wherein, based on the loading, the customer specific content is secure from extraction via the master key by at least entities other than the customer.

6. 发明申请

US20160210119A1 PIPELINED MODULAR REDUCTION AND DIVISION 有权
公开(公告)号：US20160210119A1
公开(公告)日：2016-07-21
申请号：US15090908
申请日：2016-04-05
申请人： International Business Machines Corporation
发明人： Vincenzo Condorelli , Silvio Dragone , William Santiago Fernandez , Nihad Hadzic , Andrew R. Ranck
IPC分类号： G06F5/01
CPC分类号： G06F5/01 , G06F7/72
摘要： Embodiments relate to modular reductions. An aspect includes a system to perform modular reductions. The system includes a shift register to store an input string or number. The system also includes a plurality of processing elements arranged in a pipeline configuration to convert the input string to a predefined alphabet or to convert the number to a different base based on a plurality of modular reductions, an output of one of the plurality of processing elements being an input to a subsequent one of the plurality of processing elements in the pipeline as part of a recursive division, and an input of a first one of the plurality of processing elements in the pipeline being an output of the shift register.

7. 发明申请

US20150254079A1 Code Updates in Processing Systems 有权
标题翻译：处理系统中的代码更新
公开(公告)号：US20150254079A1
公开(公告)日：2015-09-10
申请号：US14679533
申请日：2015-04-06
申请人： International Business Machines Corporation
发明人： Vincenzo Condorelli , Silvio Dragone , William Santiago-Fernandez , Tamas Visegrady
IPC分类号： G06F9/44 , G06F9/445
CPC分类号： G06F9/4403 , G05B19/056 , G06F8/63 , G06F8/65 , G06F8/654 , G06F9/4401 , G06F9/44505 , G06F11/1433 , G06F12/0246 , G06F13/4022 , G06F21/575
摘要： A method for updating code images in a system includes booting a first image of a code with a sub-system processor, receiving a second image of the code, performing a security and reliability check of the second image of the code with the sub-system processor, determining whether the security and reliability check of the second image of the code is successful, storing the second image of the code in a first memory device responsive to determining that the security and reliability check of the second image of the code is successful, designating the second image of the code as an active image, and sending the second image of the code to a second memory device, the second memory device communicatively connected with the first memory device and a main processor.
摘要翻译：一种用于更新系统中的代码图像的方法包括用子系统处理器引导代码的第一图像，接收代码的第二图像，使用子系统执行代码的第二图像的安全性和可靠性检查处理器，确定代码的第二图像的安全性和可靠性检查是否成功，将代码的第二图像存储在第一存储器设备中，以响应于确定代码的第二图像的安全性和可靠性检查成功，将代码的第二图像指定为活动图像，以及将代码的第二图像发送到第二存储器设备，与第一存储器设备和主处理器通信地连接的第二存储器设备。

8. 发明授权

US09875367B2 Customer load of field programmable gate arrays 有权
公开(公告)号：US09875367B2
公开(公告)日：2018-01-23
申请号：US15440631
申请日：2017-02-23
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Todd W. Arnold , Mark A. Check , Vincenzo Condorelli
IPC分类号： G06F21/62 , G09C1/00 , H04L9/08 , H04L9/14 , G06F21/76
CPC分类号： G06F21/62 , G06F21/6209 , G06F21/76 , G06Q20/341 , G06Q20/3552 , G06Q2220/00 , G09C1/00 , H04L9/0822 , H04L9/0877 , H04L9/14 , H04L2209/24
摘要： Customer content is securely loaded on a field programmable gate array (FPGA) located on a secure cryptography card. The customer content is loaded such that it may not be extracted. A customer obtains a secure cryptography card that includes a field programmable gate array and a master key generated by the secure cryptography card. The customer loads customer specific content on the field programmable gate array, wherein, based on the loading, the customer specific content is secure from extraction via the master key by at least entities other than the customer.

9. 发明授权

US09535656B2 Pipelined modular reduction and division 有权
标题翻译：流水线模块化减排和划分
公开(公告)号：US09535656B2
公开(公告)日：2017-01-03
申请号：US14210966
申请日：2014-03-14
申请人： International Business Machines Corporation
发明人： Vincenzo Condorelli , Silvio Dragone , William Santiago Fernandez , Nihad Hadzic , Andrew R. Ranck
IPC分类号： G06F5/01 , G06F7/72
CPC分类号： G06F5/01 , G06F7/72
摘要： Embodiments relate to modular reductions. An aspect includes a system to perform modular reductions. The system includes a shift register to store an input string or number. The system also includes a plurality of processing elements arranged in a pipeline configuration to convert the input string to a predefined alphabet or to convert the number to a different base based on a plurality of modular reductions, an output of one of the plurality of processing elements being an input to a subsequent one of the plurality of processing elements in the pipeline as part of a recursive division, and an input of a first one of the plurality of processing elements in the pipeline being an output of the shift register.
摘要翻译：实施例涉及模块化减少。一个方面包括执行模块化减少的系统。该系统包括用于存储输入字符串或数字的移位寄存器。该系统还包括以流水线配置布置的多个处理元件，用于将输入串转换成预定义的字母表，或者基于多个模块化减少将该数量转换为不同的基数，多个处理元件之一的输出作为递归分割的一部分，作为流水线中的多个处理元件中的后续处理元件的输入，并且流水线中的多个处理元件中的第一个处理元素的输入是移位寄存器的输出。

10. 发明授权

US09471276B2 Pipelined modular reduction and division 有权
标题翻译：流水线模块化减排和划分
公开(公告)号：US09471276B2
公开(公告)日：2016-10-18
申请号：US15090908
申请日：2016-04-05
申请人： International Business Machines Corporation
发明人： Vincenzo Condorelli , Silvio Dragone , William Santiago Fernandez , Nihad Hadzic , Andrew R. Ranck
IPC分类号： G06F5/01
CPC分类号： G06F5/01 , G06F7/72
摘要： Embodiments relate to modular reductions. An aspect includes a system to perform modular reductions. The system includes a shift register to store an input string or number. The system also includes a plurality of processing elements arranged in a pipeline configuration to convert the input string to a predefined alphabet or to convert the number to a different base based on a plurality of modular reductions, an output of one of the plurality of processing elements being an input to a subsequent one of the plurality of processing elements in the pipeline as part of a recursive division, and an input of a first one of the plurality of processing elements in the pipeline being an output of the shift register.
摘要翻译：实施例涉及模块化减少。一个方面包括执行模块化减少的系统。该系统包括用于存储输入字符串或数字的移位寄存器。该系统还包括以流水线配置布置的多个处理元件，用于将输入串转换成预定义的字母表，或者基于多个模块化减少将该数量转换为不同的基数，多个处理元件之一的输出作为递归分割的一部分，作为流水线中的多个处理元件中的后续处理元件的输入，并且流水线中的多个处理元件中的第一个处理元素的输入是移位寄存器的输出。

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