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1. 发明申请

US20180061800A1 REDUCTION OF SOLDER INTERCONNECT STRESS 审中-公开
公开(公告)号：US20180061800A1
公开(公告)日：2018-03-01
申请号：US15794192
申请日：2017-10-26
申请人： International Business Machines Corporation
发明人： Anson J. Call , Vijayeshwar D. Khanna , David J. Russell , Krishna R. Tunga
IPC分类号： H01L23/00 , H01L23/498 , H01L21/48
CPC分类号： H01L24/17 , H01L21/4853 , H01L23/49838 , H01L24/16 , H01L2224/16227 , H01L2224/17133 , H01L2924/3512
摘要： An electrical contact upon an interposer and/or upon a processing device includes a minor axis and a major axis. The contact is positioned such that the major axis is generally aligned with the direction of expansion of the interposer and/or the processing device. The electrical contact may further be positioned within a power/ground or input/output (I/O) region of the interposer and/or processing device. The electrical contact may further be positioned within a center region that is surrounded by a perimeter region of the interposer and/or the processing device. The dimensions or aspect ratios of major and minor axes of neighboring electrical contacts within an electrical contact grid may differ relative thereto. Further, the angle of respective major and minor axes of neighboring electrical contacts within the electrical contact grid may differ relative thereto.

2. 发明授权

US09171742B2 Alignment of integrated circuit chip stack 有权
标题翻译：集成电路芯片堆栈对齐
公开(公告)号：US09171742B2
公开(公告)日：2015-10-27
申请号：US13947543
申请日：2013-07-22
申请人： International Business Machines Corporation
发明人： Evan G. Colgan , Steven A. Cordes , Daniel C. Edelstein , Vijayeshwar D. Khanna , Kenneth Latzko , Qinghuang Lin , Peter J. Sorce , Sri M. Sri-Jayantha , Robert L. Wisnieff , Roy R. Yu
IPC分类号： H01L21/00 , H01L21/50 , H01L25/00 , H01L25/065 , H01L29/06 , H01L23/02 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/50 , H01L25/0657 , H01L25/50 , H01L29/0657 , H01L2225/06513 , H01L2225/06593 , H01L2924/0002 , H01L2924/10156 , H01L2924/00
摘要： The present disclosure relates to methods and devices for manufacturing a three-dimensional chip package. A method includes forming a linear groove on an alignment rail, attaching an alignment rod to the linear groove, forming alignment channels on a plurality of integrated circuit chips, and aligning the plurality of integrated circuit chips by stacking the plurality of integrated circuit chips along the alignment rail. Another method includes forming an alignment ridge on an alignment rail, forming alignment channels on a plurality of integrated circuit chips, and aligning the plurality of integrated circuit chips by stacking the plurality of integrated circuit chips along the alignment rail.
摘要翻译：本公开涉及用于制造三维芯片封装的方法和装置。一种方法包括在对准导轨上形成直线槽，将对准杆连接到线性槽，在多个集成电路芯片上形成对准通道，并通过将多个集成电路芯片沿着对准导轨另一种方法包括在对准导轨上形成对准脊，在多个集成电路芯片上形成对准通道，并且通过沿对准导轨堆叠多个集成电路芯片来对准多个集成电路芯片。

3. 发明申请

US20140151849A1 ELECTRONIC COMPONENTS ON TRENCHED SUBSTRATES AND METHOD OF FORMING SAME 有权
标题翻译：加固基板上的电子元件及其形成方法
公开(公告)号：US20140151849A1
公开(公告)日：2014-06-05
申请号：US14157755
申请日：2014-01-17
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： David Questad , Vijayeshwar D. Khanna , Jennifer V. Muncy , Arun Sharma , Sri M. Sri-Jayantha , Lorenzo Valdevit
IPC分类号： H01L49/02
CPC分类号： H01L28/40 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00011 , H01L2924/00014 , H01L2924/15174 , H01L2924/15311 , H05K1/0231 , H05K1/0271 , H05K1/111 , H05K3/3436 , H05K3/3442 , H05K2201/09036 , H05K2201/10015 , H05K2201/10727 , Y02P70/613 , Y10T29/4913 , Y10T428/24479 , H01L2224/0401 , H01L2924/00
摘要： An electronic module includes a substrate including at least one structure that reduces stress flow through the substrate, wherein the structure includes at least one trench in a surface of the substrate, and a plurality of capacitor legs disposed on an upper surface of the substrate.
摘要翻译：一种电子模块包括一个包括至少一个结构的衬底，该结构减少了通过衬底的应力流动，其中该结构包括衬底的表面中的至少一个沟槽和设置在衬底的上表面上的多个电容器脚。

4. 发明申请

US20180061799A1 REDUCTION OF SOLDER INTERCONNECT STRESS 审中-公开
公开(公告)号：US20180061799A1
公开(公告)日：2018-03-01
申请号：US15671955
申请日：2017-08-08
申请人： International Business Machines Corporation
发明人： Anson J. Call , Vijayeshwar D. Khanna , David J. Russell , Krishna R. Tunga
IPC分类号： H01L23/00 , H01L23/498 , H01L21/48
CPC分类号： H01L24/17 , H01L21/4853 , H01L23/49838 , H01L24/16 , H01L2224/16227 , H01L2224/17133 , H01L2924/3512
摘要： A first electrical contact and second contact is upon an interposer and/or upon a processing device. The first contact includes a minor axis and a major axis. The second contact includes diameter axes. The first contact is positioned such that the major axis is generally aligned with the direction of expansion of the interposer and/or the processing device. The first electrical contact may further be positioned within a power/ground or input/output (I/O) region of the interposer and/or processing device. The first electrical contact may further be positioned within a center region that is surrounded by a perimeter region of the interposer and/or the processing device. The dimensions or aspect ratios of major and minor axes of neighboring first electrical contacts within an electrical contact grid may differ relative thereto. Further, the angle of respective major and minor axes of neighboring first electrical contacts within the electrical contact grid may differ relative thereto.

5. 发明申请

US20200146172A1 SERVER NODE CONNNECTOR MATING CONDITION HEALTH MONITORING AND REPORTING 审中-公开
公开(公告)号：US20200146172A1
公开(公告)日：2020-05-07
申请号：US16179983
申请日：2018-11-04
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Sri M. Sri-Jayantha , Hien P. Dang , Vijayeshwar D. Khanna
IPC分类号： H05K7/14 , G08B21/18 , G01R31/04 , G01B21/22 , G01B21/16 , H01R25/00
摘要： A server node connection system uses two or more proximity sensors per server node to determine progressive, real time changes in wipe length for each individual connector on the node that is connected to an opposing header connector on header connected to a midplane of the server assembly/rack. The system is capable of scanning, monitoring, trending, and alarming.

6. 发明授权

US10108753B2 Laminate substrate thermal warpage prediction for designing a laminate substrate 有权
公开(公告)号：US10108753B2
公开(公告)日：2018-10-23
申请号：US15176101
申请日：2016-06-07
申请人： International Business Machines Corporation
发明人： Anson J. Call , Vijayeshwar D. Khanna , David J. Russell , Krishna R. Tunga
IPC分类号： G06F17/50
摘要： Method of designing a laminate substrate having upper laminate layers and an equal plurality of lower laminate layers including: dividing the laminate substrate into regions having corresponding laminate layer pairs consisting of an upper laminate layer and a lower laminate layer; calculating a net stretching value for each corresponding laminate layer pair in each region to result in net stretching values in each region; summing the net stretching values in each region to result in a net stretching value for each region proportional to a curvature of each local region; calculating a relative out-of-plane displacement for the laminate substrate from the curvature of each local region; calculating a predicted thermal warpage for the laminate substrate; and finalizing a design of the laminate substrate when the predicted thermal warpage is within a predetermined acceptable range.

7. 发明授权

US09563732B1 In-plane copper imbalance for warpage prediction 有权
标题翻译：平面铜不平衡的翘曲预测
公开(公告)号：US09563732B1
公开(公告)日：2017-02-07
申请号：US15006567
申请日：2016-01-26
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Anson J. Call , Vijayeshwar D. Khanna , David J. Russell , Krishna R. Tunga
IPC分类号： G06F17/50 , H05K3/00
CPC分类号： G06F17/5068 , G06F2217/44 , H05K1/0271 , H05K3/0005
摘要： A method of predicting warpage of a laminate is disclosed in which in-plane copper imbalance is calculated. A method of designing an organic build-up laminate is provided in which in-plane copper imbalance is calculated and imbalances are corrected.
摘要翻译：公开了一种预测层压板的翘曲的方法，其中计算了平面内的不平衡。提供一种设计有机积层叠板的方法，其中计算面内铜不平衡并校正不平衡。

8. 发明授权

US10276535B2 Method of fabricating contacts of an electronic package structure to reduce solder interconnect stress 有权
公开(公告)号：US10276535B2
公开(公告)日：2019-04-30
申请号：US15794192
申请日：2017-10-26
申请人： International Business Machines Corporation
发明人： Anson J. Call , Vijayeshwar D. Khanna , David J. Russell , Krishna R. Tunga
IPC分类号： H01L21/44 , H01L23/00 , H01L23/498 , H01L21/48
摘要： An electrical contact upon an interposer and/or upon a processing device includes a minor axis and a major axis. The contact is positioned such that the major axis is generally aligned with the direction of expansion of the interposer and/or the processing device. The electrical contact may further be positioned within a power/ground or input/output (I/O) region of the interposer and/or processing device. The electrical contact may further be positioned within a center region that is surrounded by a perimeter region of the interposer and/or the processing device. The dimensions or aspect ratios of major and minor axes of neighboring electrical contacts within an electrical contact grid may differ relative thereto. Further, the angle of respective major and minor axes of neighboring electrical contacts within the electrical contact grid may differ relative thereto.

9. 发明授权

US09630269B2 Mechanism to attach a die to a substrate 有权
公开(公告)号：US09630269B2
公开(公告)日：2017-04-25
申请号：US14066989
申请日：2013-10-30
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Vijayeshwar D. Khanna , Mohammed S. Shaikh
IPC分类号： H01L23/48 , B23K3/08 , H01L23/00 , B23K1/00 , B23K1/008 , B23K101/40
CPC分类号： B23K3/087 , B23K1/0016 , B23K1/008 , B23K2101/40 , H01L24/75 , H01L24/81 , H01L2224/13147 , H01L2224/75252 , H01L2224/75315 , H01L2224/75318 , H01L2224/75705 , H01L2224/75745 , H01L2224/81191 , H01L2224/81203 , H01L2224/81815 , H01L2924/15787 , H01L2924/00 , H01L2924/00014 , H01L2924/00012
摘要： A mechanism to attach a die to a substrate and method of use are disclosed. The vacuum carrier includes a frame composed of material compatible with solder reflow process. The vacuum carrier further includes a vacuum port extending from a top surface to an underside surface of the frame. The vacuum carrier further includes a seal mechanism provided about a perimeter on the underside surface of the frame of the vacuum carrier. The frame and seal mechanism are structured to maintain a flatness of a die attached to the vacuum carrier by a vacuum source during the solder reflow process.

10. 发明授权

US09227261B2 Vacuum carriers for substrate bonding 有权
标题翻译：用于衬底粘合的真空载体
公开(公告)号：US09227261B2
公开(公告)日：2016-01-05
申请号：US13959867
申请日：2013-08-06
申请人： International Business Machines Corporation
发明人： Vijayeshwar D. Khanna , Sri M. Sri-Jayantha
IPC分类号： B23K37/00 , B23K37/04 , B23K3/08 , B25B11/00 , B23K1/00
CPC分类号： B23K3/087 , B23K1/0016 , B23K37/0408 , B23K37/0426 , B23K37/0435 , B23K37/0443 , B25B11/005
摘要： A vacuum carrier can be employed to provide a partial vacuum on a back side surface of a substrate thereby holding the substrate flat against a rigid surface of the carrier throughout the duration of a bonding process. The magnitude of vacuum can be optimized to limit the warping of the substrate during and after bonding with another substrate, and to limit the mechanical stress induced in the solder balls during cooling. The vacuum carrier can include a base plate, a seal plate with at least one opening configured to accommodate at least one substrate, and vacuum seal elements configured to create a vacuum environment that pushes the substrate against the base plate when the vacuum carrier is under vacuum. The configuration of the vacuum carrier is chosen to avoid distortion of the substrate due to the vacuum seal elements, while allowing adjustment of the magnitude of the partial vacuum.
摘要翻译：可以使用真空载体来在基板的背面提供部分真空，从而在粘合过程的整个持续时间期间将基板平坦地抵靠载体的刚性表面。可以优化真空的大小以限制在与另一基板接合期间和之后的基板的翘曲，并且限制在冷却期间在焊球中引起的机械应力。真空载体可以包括基板，密封板，其具有构造成容纳至少一个基板的至少一个开口，以及真空密封元件，其构造成当真空载体处于真空下时产生将基板推靠在基板上的真空环境。选择真空载体的构造以避免由于真空密封元件而引起的基板变形，同时允许调整部分真空的大小。

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