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1. 发明授权

US09761679B2 Performance optimized gate structures having memory device and logic device, the memory device with silicided source/drain regions that are raised with respect to silicided source/drain regions of the logic device 有权
公开(公告)号：US09761679B2
公开(公告)日：2017-09-12
申请号：US15070154
申请日：2016-03-15
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Paul Chang , Katsunori Onishi , Jian Yu
IPC分类号： H01L29/417 , H01L21/8238 , H01L21/8234 , H01L29/66 , H01L29/45 , H01L27/088 , H01L29/08 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/78 , H01L21/02 , H01L21/308
CPC分类号： H01L29/41783 , H01L21/02362 , H01L21/3081 , H01L21/823418 , H01L21/823814 , H01L27/088 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/45 , H01L29/665 , H01L29/66636 , H01L29/7848 , H01L29/7851
摘要： A performance optimized CMOS FET structure and methods of manufacture are disclosed. The method includes forming source and drain regions for a first type device and a second type device. The method further includes lowering the source and drain regions for the first type device, while protecting the source and drain regions for the second type device. The method further includes performing silicide processes to form silicide regions on the lowered source and drain regions for the first type device and the source and drain regions for the second type device.

2. 发明授权

US09735058B2 Method of forming performance optimized gate structures by silicidizing lowered source and drain regions 有权
公开(公告)号：US09735058B2
公开(公告)日：2017-08-15
申请号：US15211742
申请日：2016-07-15
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Paul Chang , Katsunori Onishi , Jian Yu
IPC分类号： H01L21/8234 , H01L29/66 , H01L29/45 , H01L29/417 , H01L27/088 , H01L21/8238 , H01L29/08 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/78 , H01L21/02 , H01L21/308
CPC分类号： H01L29/41783 , H01L21/02362 , H01L21/3081 , H01L21/823418 , H01L21/823814 , H01L27/088 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/45 , H01L29/665 , H01L29/66636 , H01L29/7848 , H01L29/7851
摘要： A performance optimized CMOS FET structure and methods of manufacture are disclosed. The method includes forming source and drain regions for a first type device and a second type device. The method further includes lowering the source and drain regions for the first type device, while protecting the source and drain regions for the second type device. The method further includes performing silicide processes to form silicide regions on the lowered source and drain regions for the first type device and the source and drain regions for the second type device.

3. 发明申请

US20140264558A1 FACETED INTRINSIC EPITAXIAL BUFFER LAYER FOR REDUCING SHORT CHANNEL EFFECTS WHILE MAXIMIZING CHANNEL STRESS LEVELS 有权
标题翻译：面向内部外延缓冲层，用于在最大化通道应力水平时减少短路通道效应
公开(公告)号：US20140264558A1
公开(公告)日：2014-09-18
申请号：US13839741
申请日：2013-03-15
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Bhupesh Chandra , Paul Chang , Gregory G. Freeman , Dechao Guo , Judson R. Holt , Arvind Kumar , Timothy J. McArdle , Shreesh Narasimha , Viorel Ontalus , Sangameshwar Rao Saudari , Christopher D. Sheraw , Matthew W. Stoker
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7848 , H01L29/045 , H01L29/165 , H01L29/36 , H01L29/66636 , H01L29/7834
摘要： A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy. A facet adjoins each edge at which an outer sidewall of a gate spacer adjoins a sidewall of the source trench or the drain trench. A doped semiconductor material is subsequently deposited to fill the source trench and the drain trench. The doped semiconductor material can be deposited such that the facets of the intrinsic buffer semiconductor material are extended and inner sidewalls of the deposited doped semiconductor material merges in each of the source trench and the drain trench. The doped semiconductor material can subsequently grow upward. Faceted intrinsic buffer semiconductor material portions allow greater outdiffusion of dopants near faceted corners while suppressing diffusion of dopants in regions of uniform width, thereby suppressing short channel effects.
摘要翻译：通过选择性外延法将刻面的本征缓冲半导体材料沉积在源沟槽和漏极沟槽的侧壁上。一个刻面邻接每个边缘，栅极间隔件的外侧壁邻接源沟槽或漏极沟槽的侧壁。随后沉积掺杂的半导体材料以填充源极沟槽和漏极沟槽。可以沉积掺杂的半导体材料，使得本征缓冲半导体材料的面被延伸，并且沉积的掺杂半导体材料的内壁在源极沟槽和漏极沟槽的每一个中融合。掺杂的半导体材料随后可以向上生长。方面的本征缓冲半导体材料部分允许在均匀宽度的区域中抑制掺杂剂的扩散，从而抑制短沟道效应，从而在小角部附近进一步扩散掺杂剂。

4. 发明授权

US08796742B1 Non-replacement gate nanomesh field effect transistor with epitixially grown source and drain 有权
标题翻译：具有上限生长的源极和漏极的非替代栅极纳米场效应晶体管
公开(公告)号：US08796742B1
公开(公告)日：2014-08-05
申请号：US14022735
申请日：2013-09-10
申请人： International Business Machines Corporation
发明人： Josephine B. Chang , Paul Chang , Isaac Lauer , Jeffrey W. Sleight
IPC分类号： H01L29/745 , H01L29/74 , H01L21/336
CPC分类号： H01L29/0673 , B82Y10/00 , B82Y40/00 , H01L29/16 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78696
摘要： An alternating stack of two different semiconductor materials is patterned to include two pad regions and nanowire regions. A semiconductor material is laterally etched selective to another semiconductor material to form a nanomesh including suspended semiconductor nanowires. Gate dielectrics, a gate electrode, and a gate cap dielectric are formed over the nanomesh. A dielectric spacer is formed around the gate electrode. The semiconductor materials in the two pad regions and physically exposed portions of the nanomesh are removed employing the dielectric spacer and the gate cap dielectric as an etch mask. A source region and a drain region are epitaxially grown from end surfaces of the nanomesh.
摘要翻译：将两个不同的半导体材料的交替堆叠图案化以包括两个焊盘区域和纳米线区域。对另一半导体材料的半导体材料进行横向蚀刻选择性以形成包括悬浮半导体纳米线的纳米片。在纳米级上形成栅极电介质，栅电极和栅极帽电介质。在栅电极周围形成介电隔离件。使用电介质间隔物和栅极盖电介质作为蚀刻掩模去除两个焊盘区域中的半导体材料和纳米薄膜的物理暴露部分。源极区域和漏极区域从纳米单体的端面外延生长。

5. 发明授权

US08785981B1 Non-replacement gate nanomesh field effect transistor with pad regions 有权
公开(公告)号：US08785981B1
公开(公告)日：2014-07-22
申请号：US14022469
申请日：2013-09-10
申请人： International Business Machines Corporation
发明人： Josephine B. Chang , Paul Chang , Isaac Lauer , Jeffrey W. Sleight
IPC分类号： H01L29/745 , H01L21/336
CPC分类号： H01L29/775 , B82Y10/00 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66469 , H01L29/78696
摘要： A gate-first processing scheme for forming a nanomesh field effect transistor is provided. An alternating stack of two different semiconductor materials is patterned to include two pad regions and nanowire regions. A semiconductor material is laterally etched selective to another semiconductor material to form a nanomesh including suspended semiconductor nanowires. A stack of a gate dielectric, a gate electrode, and a gate cap dielectric is formed over the nanomesh. A dielectric spacer is formed around the gate electrode. An isotropic etch is employed to remove dielectric materials that are formed in lateral recesses of the patterned alternating stack. A selective epitaxy process can be employed to form a source region and a drain region.

6. 发明授权

US08778768B1 Non-replacement gate nanomesh field effect transistor with epitixially grown source and drain 有权
公开(公告)号：US08778768B1
公开(公告)日：2014-07-15
申请号：US13796418
申请日：2013-03-12
申请人： International Business Machines Corporation
发明人： Josephine B. Chang , Paul Chang , Issac Lauer , Jeffrey W. Sleight
IPC分类号： H01L21/336 , H01L29/745
CPC分类号： H01L29/0673 , B82Y10/00 , B82Y40/00 , H01L29/16 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78696
摘要： An alternating stack of two different semiconductor materials is patterned to include two pad regions and nanowire regions. A semiconductor material is laterally etched selective to another semiconductor material to form a nanomesh including suspended semiconductor nanowires. Gate dielectrics, a gate electrode, and a gate cap dielectric are formed over the nanomesh. A dielectric spacer is formed around the gate electrode. The semiconductor materials in the two pad regions and physically exposed portions of the nanomesh are removed employing the dielectric spacer and the gate cap dielectric as an etch mask. A source region and a drain region are epitaxially grown from end surfaces of the nanomesh.

7. 发明申请

US20140123097A1 COMPACT MODEL FOR DEVICE/CIRCUIT/CHIP LEAKAGE CURRENT (IDDQ) CALCULATION INCLUDING PROCESS INDUCED UPLIFT FACTORS 有权
标题翻译：用于器件/电路/芯片泄漏电流（IDDQ）的紧凑型模型包括工艺引起的升级因素
公开(公告)号：US20140123097A1
公开(公告)日：2014-05-01
申请号：US14148234
申请日：2014-01-06
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Paul Chang , Jie Deng , Terrence B. Hook , Sim Y. Loo , Anda C. Mocuta , Jeae-Eun Park , Kern Rim , Xiaojun Yu
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G01R31/2848 , G01R31/3008 , G06F17/5009 , G06F17/5022 , G06F17/5036
摘要： A system, method and computer program product for implementing a quiescent current leakage specific model into semiconductor device design and circuit design flows. The leakage model covers all device geometries with wide temperature and voltage ranges and, without the need for stacking factor calculations nor spread sheet based IDDQ calculations. The leakage model for IDDQ calculation incorporates further parasitic and proximity effects. The leakage model implements leakage calculations at different levels of testing, e.g., from a single device to a full chip design, and are integrated within one single model. The leakage model implements leakage calculations at different levels of testing with the leverage of a single switch setting. The implementation is via a hardware definition language code or object oriented code that can be compiled and operated using a netlist of interest, e.g., for conducting a performance analysis.
摘要翻译：一种用于将静态电流泄漏特定模型实现为半导体器件设计和电路设计流程的系统，方法和计算机程序产品。泄漏模型涵盖宽温度和电压范围的所有器件几何，并且不需要堆叠因子计算，也不需要基于平板的IDDQ计算。 IDDQ计算的泄漏模型包含进一步的寄生和邻近效应。泄漏模型在不同的测试水平下实施泄漏计算，例如从单个设备到全芯片设计，并且集成在一个单一的模型中。泄漏模型通过单个开关设置的杠杆来实现不同测试级别的泄漏计算。该实现是通过硬件定义语言代码或面向对象的代码，其可以使用感兴趣的网表来编译和操作，例如用于进行性能分析。

8. 发明申请

US20140065774A1 EMBEDDED PLANAR SOURCE/DRAIN STRESSORS FOR A FINFET INCLUDING A PLURALITY OF FINS 有权
标题翻译：嵌入式平面电源/漏极应力器，包括多个FINS
公开(公告)号：US20140065774A1
公开(公告)日：2014-03-06
申请号：US14076387
申请日：2013-11-11
申请人： International Business Machines Corporation
发明人： Josephine B. Chang , Paul Chang , Michael A. Guillorn , Jeffrey W. Sleight
IPC分类号： H01L29/66
CPC分类号： H01L29/66484 , H01L21/845 , H01L27/1211 , H01L29/66795 , H01L29/7831 , H01L29/7848 , H01L29/785
摘要： Fin-defining mask structures are formed over a semiconductor material layer having a first semiconductor material and a disposable gate structure is formed thereupon. A gate spacer is formed around the disposable gate structure and physically exposed portions of the fin-defining mask structures are subsequently removed. The semiconductor material layer is recessed employing the disposable gate structure and the gate spacer as an etch mask to form recessed semiconductor material portions. Embedded planar source/drain stressors are formed on the recessed semiconductor material portions by selective deposition of a second semiconductor material having a different lattice constant than the first semiconductor material. After formation of a planarization dielectric layer, the disposable gate structure is removed. A plurality of semiconductor fins are formed employing the fin-defining mask structures as an etch mask. A replacement gate structure is formed on the plurality of semiconductor fins.
摘要翻译：翅片限定掩模结构形成在具有第一半导体材料的半导体材料层上，并且在其上形成一次性栅极结构。在一次性栅极结构周围形成栅极间隔物，随后去除鳍状物限定掩模结构的物理暴露部分。使用一次性栅极结构和栅极间隔物作为蚀刻掩模来凹入半导体材料层以形成凹入的半导体材料部分。通过选择性沉积具有与第一半导体材料不同的晶格常数的第二半导体材料，在凹入的半导体材料部分上形成嵌入式平面源极/漏极应力。在形成平坦化介电层之后，去除一次性栅极结构。使用鳍状限定掩模结构作为蚀刻掩模形成多个半导体鳍。在多个半导体鳍片上形成替换栅极结构。

9. 发明授权

US08940595B2 Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels 有权
标题翻译：方面的本征外延缓冲层，用于减少短通道效应，同时最大化通道应力水平
公开(公告)号：US08940595B2
公开(公告)日：2015-01-27
申请号：US13839741
申请日：2013-03-15
申请人： International Business Machines Corporation
发明人： Bhupesh Chandra , Paul Chang , Gregory G. Freeman , Dechao Guo , Judson R. Holt , Arvind Kumar , Timothy J. McArdle , Shreesh Narasimha , Viorel Ontalus , Sangameshwar Rao Saudari , Christopher D. Sheraw , Matthew W. Stoker
IPC分类号： H01L21/336 , H01L29/78 , H01L29/66
CPC分类号： H01L29/7848 , H01L29/045 , H01L29/165 , H01L29/36 , H01L29/66636 , H01L29/7834
摘要： A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy. A facet adjoins each edge at which an outer sidewall of a gate spacer adjoins a sidewall of the source trench or the drain trench. A doped semiconductor material is subsequently deposited to fill the source trench and the drain trench. The doped semiconductor material can be deposited such that the facets of the intrinsic buffer semiconductor material are extended and inner sidewalls of the deposited doped semiconductor material merges in each of the source trench and the drain trench. The doped semiconductor material can subsequently grow upward. Faceted intrinsic buffer semiconductor material portions allow greater outdiffusion of dopants near faceted corners while suppressing diffusion of dopants in regions of uniform width, thereby suppressing short channel effects.
摘要翻译：通过选择性外延法将刻面的本征缓冲半导体材料沉积在源沟槽和漏极沟槽的侧壁上。一个刻面邻接每个边缘，栅极间隔件的外侧壁邻接源沟槽或漏极沟槽的侧壁。随后沉积掺杂的半导体材料以填充源极沟槽和漏极沟槽。可以沉积掺杂的半导体材料，使得本征缓冲半导体材料的面被延伸，并且沉积的掺杂半导体材料的内壁在源极沟槽和漏极沟槽的每一个中融合。掺杂的半导体材料随后可以向上生长。方面的本征缓冲半导体材料部分允许在均匀宽度的区域中抑制掺杂剂的扩散，从而抑制短沟道效应，从而在小角部附近进一步扩散掺杂剂。

10. 发明申请

US20140315363A1 6T SRAM Architecture For Gate-All-Around Nanowire Devices 有权
标题翻译： 6T SRAM架构，用于门极全能纳米线器件
公开(公告)号：US20140315363A1
公开(公告)日：2014-10-23
申请号：US13970663
申请日：2013-08-20
申请人： International Business Machines Corporation
发明人： Karthik Balakrishnan , Josephine B. Chang , Paul Chang , Michael A. Guillorn
IPC分类号： H01L27/11 , H01L29/06
CPC分类号： H01L29/0673 , H01L21/84 , H01L27/092 , H01L27/1108 , H01L27/1203 , H01L29/42392 , H01L29/775
摘要： A memory device includes a first plurality of semiconductor nanowires tethered between landing pads and suspended over a substrate. A first gate electrode surrounds each of the first plurality of semiconductor nanowires, making them gate-all-around, (GAA) semiconductor nanowires. First, second, and third field effect transistors (FETs) are formed by the first plurality of semiconductor nanowires. The memory device also includes a second plurality of semiconductor nanowires tethered between landing pads and suspended over the substrate. A second gate electrode surrounds each of the second plurality of semiconductor nanowires, making them GAA semiconductor nanowires. Fourth, fifth, and sixth FETs are formed by the second plurality of semiconductor nanowires. The first gate electrode is aligned with and cross-coupled to a landing pad of the second plurality of semiconductor nanowires, and the second gate electrode is aligned with and cross-coupled to a landing pad of the first plurality of semiconductor nanowires.
摘要翻译：存储器件包括连接在着陆焊盘之间并悬挂在衬底上的第一多个半导体纳米线。第一栅电极围绕第一多个半导体纳米线中的每一个，使得它们成为栅极全绕（GAA）半导体纳米线。第一，第二和第三场效应晶体管（FET）由第一多个半导体纳米线形成。存储器件还包括拴在着陆焊盘之间并悬挂在衬底上的第二多个半导体纳米线。第二栅电极围绕第二多个半导体纳米线中的每一个，使其成为GAA半导体纳米线。第四，第五和第六FET由第二多个半导体纳米线形成。第一栅极电极与第二多个半导体纳米线的层叠焊盘对准并交叉耦合，并且第二栅极电极与第一多个半导体纳米线的焊盘对准并交叉耦合。

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