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1. 发明申请

US20170228195A1 MANAGING A COLLECTION OF DATA 有权
公开(公告)号：US20170228195A1
公开(公告)日：2017-08-10
申请号：US15495267
申请日：2017-04-24
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Jane H. Bartik , Lisa C. Heller , Damian L. Osisek , Donald W. Schmidt , Patrick M. West, JR. , Phil C. Yeh
IPC分类号： G06F3/06 , G06F13/24
CPC分类号： G06F3/0656 , G06F3/061 , G06F3/0619 , G06F3/0653 , G06F3/0673 , G06F9/30145 , G06F12/06 , G06F12/0802 , G06F13/24 , G06F2212/461
摘要： A measurement sampling facility takes snapshots of the central processing unit (CPU) on which it is executing at specified sampling intervals to collect data relating to tasks executing on the CPU. The collected data is stored in a buffer, and at selected times, an interrupt is provided to remove data from the buffer to enable reuse thereof. The interrupt is not taken after each sample, but in sufficient time to remove the data and minimize data loss.

2. 发明申请

US20170364328A1 CHECKSUM ADDER 有权
公开(公告)号：US20170364328A1
公开(公告)日：2017-12-21
申请号：US15698026
申请日：2017-09-07
申请人： International Business Machines Corporation
发明人： James R. Cuffney , John G. Rell, JR. , Eric M. Schwarz , Patrick M. West, JR.
IPC分类号： G06F7/501 , H03M7/30 , G06F7/50
CPC分类号： G06F7/5016 , G06F7/50 , H03M7/30
摘要： Embodiments relate to a hardware circuit that is operable as a fixed point adder and a checksum adder. An aspect includes a driving of a multifunction compression tree disposed on a circuit path based on a control bit to execute one of first and second schemes of vector input addition and a driving of a multifunction adder disposed on the circuit path based on the control bit to perform the one of the first and second schemes of vector input addition.

3. 发明申请

US20160210182A1 STRING DATAFLOW ERROR DETECTION 有权
标题翻译： STRING数据流错误检测
公开(公告)号：US20160210182A1
公开(公告)日：2016-07-21
申请号：US14982005
申请日：2015-12-29
申请人： International Business Machines Corporation
发明人： James R. Cuffney , Timothy J. Koprowski , John G. Rell, JR. , Patrick M. West, JR.
IPC分类号： G06F11/07
CPC分类号： G06F11/079 , G06F11/0727 , G06F11/073 , G06F11/0751 , G06F11/1048 , G06F17/16 , H03K19/20 , H04L49/555
摘要： An apparatus for comparing strings comprises a first and a second set of input registers, a matrix of comparator circuits wherein rows of the matrix correspond to the first set of input registers and columns of the matrix correspond to the second set of input registers, a set of row control registers wherein each register corresponds to a row of the matrix of the comparator circuits, the matrix of comparator circuits configured to compare data provided by the first set of registers with data provided by the second set of registers according to the row control registers, and an error detection circuit configured to compare results from four comparator circuits corresponding to two adjacent rows and two columns of the matrix of comparator circuits. A method that invokes the above mentioned apparatus is also disclosed herein, along with a computer program product corresponding to the method.
摘要翻译：一种用于比较串的装置包括第一和第二组输入寄存器，比较器电路的矩阵，其中矩阵的行对应于第一组输入寄存器，矩阵的列对应于第二组输入寄存器，一组的行控制寄存器，其中每个寄存器对应于比较器电路的矩阵行，比较器电路的矩阵被配置为将由第一组寄存器提供的数据与根据行控制寄存器的第二组寄存器提供的数据进行比较以及错误检测电路，被配置为比较对应于比较器电路的矩阵的两个相邻行和两列的四个比较器电路的结果。本文还公开了调用上述装置的方法以及与该方法对应的计算机程序产品。

4. 发明申请

US20130332709A1 SET SAMPLING CONTROLS INSTRUCTION 有权
标题翻译：设置采样控制指令
公开(公告)号：US20130332709A1
公开(公告)日：2013-12-12
申请号：US13966764
申请日：2013-08-14
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Jane H. Bartik , Lisa C. Heller , Damian L. Osisek , Donald W. Schmidt , Patrick M. West, JR. , Phil C. Yeh
IPC分类号： G06F9/30
CPC分类号： G06F3/0656 , G06F3/061 , G06F3/0619 , G06F3/0653 , G06F3/0673 , G06F9/30145 , G06F12/06 , G06F12/0802 , G06F13/24 , G06F2212/461
摘要： A measurement sampling facility takes snapshots of the central processing unit (CPU) on which it is executing at specified sampling intervals to collect data relating to tasks executing on the CPU. The collected data is stored in a buffer, and at selected times, an interrupt is provided to remove data from the buffer to enable reuse thereof. The interrupt is not taken after each sample, but in sufficient time to remove the data and minimize data loss.
摘要翻译：测量采样设备以指定的采样间隔拍摄正在其中执行的中央处理单元（CPU）的快照，以收集与在CPU上执行的任务有关的数据。收集的数据被存储在缓冲器中，并且在选定的时间提供中断以从缓冲器中移除数据以使其能够重复使用。在每个采样之后不采取中断，但是在足够的时间去除数据并最小化数据丢失。

5. 发明申请

US20170052763A1 CHECKSUM ADDER 有权
公开(公告)号：US20170052763A1
公开(公告)日：2017-02-23
申请号：US15344854
申请日：2016-11-07
申请人： International Business Machines Corporation
发明人： James R. Cuffney , John G. Rell, JR. , Eric M. Schwarz , Patrick M. West, JR.
IPC分类号： G06F7/501 , H03M7/30
CPC分类号： G06F7/5016 , G06F7/50 , H03M7/30
摘要： Embodiments relate to a hardware circuit that is operable as a fixed point adder and a checksum adder. An aspect includes a driving of a multifunction compression tree disposed on a circuit path based on a control bit to execute one of first and second schemes of vector input addition and a driving of a multifunction adder disposed on the circuit path based on the control bit to perform the one of the first and second schemes of vector input addition.
摘要翻译：实施例涉及可用作固定点加法器和校验和加法器的硬件电路。一个方面包括基于控制位驱动设置在电路路径上的多功能压缩树，以执行向量输入相加的第一和第二方案之一以及基于控制位到电路路径上的多功能加法器的驱动执行向量输入加法的第一和第二方案之一。

6. 发明申请

US20150261504A1 VECTORIZED GALOIS FIELD MULTIPLICATION 有权
标题翻译： VECTORIZED GALOIS场多项式
公开(公告)号：US20150261504A1
公开(公告)日：2015-09-17
申请号：US14291942
申请日：2014-05-30
申请人： International Business Machines Corporation
发明人： James R. Cuffney , John G. Rell, JR. , Eric M. Schwarz , Patrick M. West, JR.
IPC分类号： G06F7/72
CPC分类号： G06F7/724 , G06F2207/72
摘要： Embodiments relate to vectorized Galois field multiplication. An aspect includes an input of first and second input operands of equal sizes into a single hardware tree, a calculation of a predicted parity as a parity of the first input operand ANDed with a parity of the second input operand, a comparison of the predicted parity with a parity generated on a final result of a Galois field multiplication of the first and second operands and a raising of an error based on a mismatch between the predicted parity and the generated parity.
摘要翻译：实施例涉及矢量化伽罗瓦域乘法。一方面包括将具有相同大小的第一和第二输入操作数输入到单个硬件树中，将预测奇偶校验作为第一输入操作数的奇偶校验与第二输入操作数的奇偶校验进行运算，预测奇偶校验的比较具有在第一和第二操作数的伽罗瓦域乘法的最终结果上产生的奇偶校验，以及基于预测奇偶校验和产生的奇偶校验之间的不匹配引起的误差的增加。

7. 发明申请

US20150261501A1 CHECKSUM ADDER 有权
公开(公告)号：US20150261501A1
公开(公告)日：2015-09-17
申请号：US14211383
申请日：2014-03-14
申请人： International Business Machines Corporation
发明人： James R. Cuffney , John G. Rell, JR. , Eric M. Schwarz , Patrick M. West, JR.
IPC分类号： G06F7/50 , H03M7/30
CPC分类号： G06F7/5016 , G06F7/50 , H03M7/30
摘要： Embodiments relate to a hardware circuit that is operable as a fixed point adder and a checksum adder. An aspect includes a driving of a multifunction compression tree disposed on a circuit path based on a control bit to execute one of first and second schemes of vector input addition and a driving of a multifunction adder disposed on the circuit path based on the control bit to perform the one of the first and second schemes of vector input addition.
摘要翻译：实施例涉及可用作固定点加法器和校验和加法器的硬件电路。一个方面包括基于控制位驱动设置在电路路径上的多功能压缩树，以执行矢量输入相加的第一和第二方案之一以及基于控制位到电路路径上的多功能加法器的驱动执行向量输入加法的第一和第二方案之一。

8. 发明申请

US20210263829A1 VIRTUALIZATION OF A CENTRAL PROCESSING UNIT MEASUREMENT FACILITY 有权
公开(公告)号：US20210263829A1
公开(公告)日：2021-08-26
申请号：US17314179
申请日：2021-05-07
申请人： International Business Machines Corporation
发明人： Lisa Cranton Heller , Patrick M. West, JR. , Phil C. Yeh
IPC分类号： G06F11/34 , G06Q20/12 , G06F9/455
摘要： A central processing unit measurement facility is virtualized in order to support concurrent use of the facility by multiple guests executing within a virtual environment. Each guest of the environment has independent control over disablement/enablement of the facility for that guest.

9. 发明申请

US20160342442A1 VIRTUALIZATION OF A CENTRAL PROCESSING UNIT MEASUREMENT FACILITY 审中-公开
标题翻译：中央处理单位测量设施虚拟化
公开(公告)号：US20160342442A1
公开(公告)日：2016-11-24
申请号：US15228817
申请日：2016-08-04
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Lisa Cranton Heller , Patrick M. West, JR. , Phil C. Yeh
IPC分类号： G06F9/455 , G06F11/34
CPC分类号： G06F9/45558 , G06F11/3466 , G06F2009/45591 , G06F2201/815 , G06F2201/88 , G06Q20/1235
摘要： A central processing unit measurement facility is virtualized in order to support concurrent use of the facility by multiple guests executing within a virtual environment. Each guest of the environment has independent control over disablement/enablement of the facility for that guest.
摘要翻译：中央处理单元测量设备被虚拟化，以便支持在虚拟环境中执行的多个客户机同时使用该设施。环境的每个客人都可以独立控制该客人的设施的停用/启用。

10. 发明申请

US20160179468A1 CHECKSUM ADDER 有权
公开(公告)号：US20160179468A1
公开(公告)日：2016-06-23
申请号：US15066599
申请日：2016-03-10
申请人： International Business Machines Corporation
发明人： James R. Cuffney , John G. Rell, JR. , Eric M. Schwarz , Patrick M. West, JR.
IPC分类号： G06F7/50 , H03M7/30
CPC分类号： G06F7/5016 , G06F7/50 , H03M7/30
摘要： Embodiments relate to a hardware circuit that is operable as a fixed point adder and a checksum adder. An aspect includes a driving of a multifunction compression tree disposed on a circuit path based on a control bit to execute one of first and second schemes of vector input addition and a driving of a multifunction adder disposed on the circuit path based on the control bit to perform the one of the first and second schemes of vector input addition.

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