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1. 发明授权

US10585668B2 Processor testing using randomly generated branch instructions 有权
公开(公告)号：US10585668B2
公开(公告)日：2020-03-10
申请号：US15722938
申请日：2017-10-02
申请人： International Business Machines Corporation
发明人： Abhishek Bansal , Nitin P. Gupta , Brad L. Herold , Jayakumar N. Sankarannair
IPC分类号： G06F9/30 , G06F11/28 , G06F9/38 , G06F11/22
摘要： A process for processor testing includes generating a set of test instructions having a first portion and a second portion. A first branch instruction is randomly generated for the first portion where the first branch instruction branches to a respective instruction in a second portion by a branching location offset. A second branch instruction is randomly generated for the second portion where the second branch instruction branches to a respective instruction in the first portion by the branching location offset. If additional instructions are to be added to the set of test instructions, a value of the branching location offset is incrementing by a predetermined amount.

2. 发明申请

US20180024833A1 PROCESSOR TESTING 审中-公开
公开(公告)号：US20180024833A1
公开(公告)日：2018-01-25
申请号：US15722938
申请日：2017-10-02
申请人： International Business Machines Corporation
发明人： Abhishek Bansal , Nitin P. Gupta , Brad L. Herold , Jayakumar N. Sankarannair
IPC分类号： G06F9/30 , G06F11/22 , G06F9/38 , G06F11/28
CPC分类号： G06F9/30058 , G06F9/3005 , G06F9/3804 , G06F11/2236 , G06F11/28
摘要： A process for processor testing includes generating a set of test instructions having a first portion and a second portion. A first branch instruction is randomly generated for the first portion where the first branch instruction branches to a respective instruction in a second portion by a branching location offset. A second branch instruction is randomly generated for the second portion where the second branch instruction branches to a respective instruction in the first portion by the branching location offset. If additional instructions are to be added to the set of test instructions, a value of the branching location offset is incrementing by a predetermined amount.

3. 发明申请

US20200167159A1 PROCESSOR TESTING 审中-公开
公开(公告)号：US20200167159A1
公开(公告)日：2020-05-28
申请号：US16776041
申请日：2020-01-29
申请人： International Business Machines Corporation
发明人： Abhishek Bansal , Nitin P. Gupta , Brad L. Herold , Jayakumar N. Sankarannair
IPC分类号： G06F9/30 , G06F9/38 , G06F11/28 , G06F11/22
摘要： A process for processor testing includes dividing a memory space into first and second portions and generating first and second sets of test instructions for the respective first and second portion. The first and second sets each include a plurality of counter increment/branch instruction pairs where each branch instruction of the first set branches to a backward instruction location and each branch instruction of the second set branches to a forward instruction location.

4. 发明授权

US09785439B2 Processor testing 有权
公开(公告)号：US09785439B2
公开(公告)日：2017-10-10
申请号：US14475606
申请日：2014-09-03
申请人： International Business Machines Corporation
发明人： Abhishek Bansal , Nitin P. Gupta , Brad L. Herold , Jayakumar N. Sankarannair
IPC分类号： G06F9/30 , G06F9/38 , G06F11/22 , G06F11/28
CPC分类号： G06F9/30058 , G06F9/3005 , G06F9/3804 , G06F11/2236 , G06F11/28
摘要： Processors may be tested according to various implementations. In one general implementation, a process for processor testing may include randomly generating a first plurality of branch instructions for a first portion of an instruction set, each branch instruction in the first portion branching to a respective instruction in a second portion of the instruction set. The process may also include randomly generating a second plurality of branch instructions for the second portion of the instruction set, each branch instruction in the second portion branching to a respective instruction in the first portion of the instruction set. The process may additionally include generating a plurality of instructions to increment a counter when each branch instruction is encountered during execution.

5. 发明申请

US20150026445A1 PROCESSOR TESTING 有权
标题翻译：处理器测试
公开(公告)号：US20150026445A1
公开(公告)日：2015-01-22
申请号：US14475606
申请日：2014-09-03
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Abhishek Bansal , Nitin P. Gupta , Brad L. Herold , Jayakumar N. Sankarannair
IPC分类号： G06F9/30
CPC分类号： G06F9/30058 , G06F9/3005 , G06F9/3804 , G06F11/2236 , G06F11/28
摘要： Processors may be tested according to various implementations. In one general implementation, a process for processor testing may include randomly generating a first plurality of branch instructions for a first portion of an instruction set, each branch instruction in the first portion branching to a respective instruction in a second portion of the instruction set. The process may also include randomly generating a second plurality of branch instructions for the second portion of the instruction set, each branch instruction in the second portion branching to a respective instruction in the first portion of the instruction set. The process may additionally include generating a plurality of instructions to increment a counter when each branch instruction is encountered during execution.
摘要翻译：处理器可以根据各种实现来测试。在一般的实现中，用于处理器测试的过程可以包括随机生成用于指令集的第一部分的第一多个分支指令，第一部分中的每个分支指令分支到指令集的第二部分中的相应指令。该过程还可以包括随机地生成用于指令集的第二部分的第二多个分支指令，第二部分中的每个分支指令分支到指令集的第一部分中的相应指令。该过程可以另外包括在执行期间遇到每个分支指令时产生多个指令来增加计数器。

6. 发明授权

US11036507B2 Processor testing using pairs of counter incrementing and branch instructions 有权
公开(公告)号：US11036507B2
公开(公告)日：2021-06-15
申请号：US16776041
申请日：2020-01-29
申请人： International Business Machines Corporation
发明人： Abhishek Bansal , Nitin P. Gupta , Brad L. Herold , Jayakumar N. Sankarannair
IPC分类号： G06F9/30 , G06F9/38 , G06F11/28 , G06F11/22
摘要： A process for processor testing includes dividing a memory space into first and second portions and generating first and second sets of test instructions for the respective first and second portion. The first and second sets each include a plurality of counter increment/branch instruction pairs where each branch instruction of the first set branches to a backward instruction location and each branch instruction of the second set branches to a forward instruction location.

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