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1. 发明授权

US11916568B2 Sampling circuit with a hierarchical time step generator 有权
公开(公告)号：US11916568B2
公开(公告)日：2024-02-27
申请号：US17652960
申请日：2022-03-01
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Marcel A. Kossel , Pier Andrea Francese , Abdullah Serdar Yonar , Mridula Prathapan , Thomas Morf
IPC分类号： H03M1/50 , H03K5/135
CPC分类号： H03M1/50 , H03K5/135
摘要： A hierarchical time step generator circuit is configured to be used for a time-based analog-to-digital converter. The hierarchical time step generator is configured to generate multiphase clock signals in response to receiving a reference clock signal. The time-based analog-to-digital converter is configured to be controlled to digitize the input signal by the multiphase clock signals. The hierarchical time step generator includes a first level time step generator configured to generate the a set of first level multiphase signals in response to receiving the reference clock signal a phase interpolator circuit configured as second level to generate second level clock signals between each of the first level clock signals and a third level configured to generate the third set of multiphase clock signals using a set of time staggered multi-phase phase locked loops synchronized to each of the second level clock signals.

2. 发明授权

US11811418B2 Analog-to-digital converter circuit with a nested look up table 有权
公开(公告)号：US11811418B2
公开(公告)日：2023-11-07
申请号：US17652957
申请日：2022-03-01
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Marcel A. Kossel , Pier Andrea Francese , Abdullah Serdar Yonar , Mridula Prathapan , Thomas Morf
IPC分类号： H03M1/12 , H04B1/16
CPC分类号： H03M1/124 , H03M1/121 , H04B1/16
摘要： Disclosed herein is an analog-to-digital converter circuit configured for digitizing an analog input signal. The analog-to-digital converter comprises an analog input configured for receiving the analog input signal. The analog-to-digital converter circuit further comprises at least one sub-ADC connected to the analog input signal, wherein the at least one sub-ADC is configured to output at least one encoded output vector in response to receiving the analog input signal. The analog-to-digital converter circuit further comprises a lookup circuit comprising a nested lookup table. The lookup circuit is configured to select an output value from the nested lookup table using the at least one encoded output vector, wherein the lookup circuit is configured to provide the output value as the digitization of the analog input signal.

3. 发明申请

US20230139805A1 CONTROL UNIT FOR QUBITS 有权
公开(公告)号：US20230139805A1
公开(公告)日：2023-05-04
申请号：US17453499
申请日：2021-11-04
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Thomas Morf , Cezar Bogdan Zota , Peter Mueller , Pier Andrea Francese , Marcel A. Kossel , Matthias Braendli , Mridula Prathapan
IPC分类号： G06F15/82 , G06N10/40
摘要： The invention relates to a control unit for controlling a data transfer between a classical processor and a quantum processor with a plurality of qubits. The control unit comprises a plurality of control and read-out circuits configured for controlling and reading out the plurality of qubits. Each of the control and read-out circuits is assigned to one or more of the qubits. A controlling of the quantum processor by the control unit comprises selectively powering on a subset of the control and read-out circuits during an instruction cycle, while ensuring that the remaining control and read-out circuits are powered off during the instruction cycle. The powered-on subset of control and read-out circuits is used to control a subset of the qubits and to read out data from the subset of qubits.

4. 发明授权

US10943653B2 Memory receiver with resistive voltage divider 有权
公开(公告)号：US10943653B2
公开(公告)日：2021-03-09
申请号：US16108207
申请日：2018-08-22
申请人： International Business Machines Corporation
发明人： Marcel A. Kossel
IPC分类号： G11C13/00 , H03F1/02 , H03F3/45 , G05F3/08 , G11C7/10 , G06F3/06 , G06F13/16 , H03M1/12
摘要： A receiver circuit is configured to receive input signals having a first reference voltage level. The first reference voltage level is a first logical high voltage level. The receiver circuit comprises an input stage comprising a resistive voltage divider. The resistive voltage divider is configured to convert the input signals having the first reference voltage level to input signals having a second reference voltage level. The second reference voltage level is a second logical high voltage level. The receiver circuit comprises a preamplifier configured to receive and amplify the input signals having the second reference voltage level.

5. 发明授权

US10454723B1 Decision feedback equalizer 有权
公开(公告)号：US10454723B1
公开(公告)日：2019-10-22
申请号：US16033704
申请日：2018-07-12
申请人： International Business Machines Corporation
发明人： Marcel A. Kossel , Vishal Khatri
IPC分类号： H03H7/30 , H04L25/03 , G11C11/4093 , G11C11/4076
摘要： Embodiments relate to a decision feedback equalizer configured for a half-rate operation. The decision feedback equalizer includes a single summer stage and a direct feedback path configured to provide feedback to the single summer stage. The decision feedback equalizer further includes an even sampler configured to sample even data of an output signal of the single summer stage, an odd sampler configured to sample odd data of the output signal of the single summer stage and a plurality of 2:1 multiplexers arranged in the direct feedback path. The plurality of 2:1 multiplexers are configured to feed the even and odd data in an alternating manner back to the single summer stage, thereby adapting the feedback to the half-rate operation of the decision feedback equalizer. A corresponding memory system and design structure are also provided.

6. 发明授权

US08692600B1 Multi-protocol driver slew rate calibration system for calibration slew rate control signal values 有权
标题翻译：多协议驱动器转换速率校准系统，用于校准转换速率控制信号值
公开(公告)号：US08692600B1
公开(公告)日：2014-04-08
申请号：US13737110
申请日：2013-01-09
申请人： International Business Machines Corporation
发明人： Rafael Blanco , Marcel A. Kossel , Michael A. Sorna
IPC分类号： H03K5/12
CPC分类号： H03K5/135
摘要： Multi-protocol driver slew rate calibration systems for calibrating slew rate control signal values are provided. Embodiments include generating, by a first phase rotator, a first clock signal; generating, by the second phase rotator, a second clock signal; initially setting, by a calibration controller, phase selector amounts such that the first clock signal is delayed relative to the second clock signal; determining whether the first clock signal is delayed relative to the second clock signal; if the first clock signal is delayed, changing the second phase selector amount; and if the first clock signal is not delayed, using the first clock signal and the second clock signal to calibrate values of control signals provided to control a slew rate of a calibration clock delay line such that the slew rate of the calibration clock delay line substantially matches a target slew rate.
摘要翻译：提供了用于校准转换速率控制信号值的多协议驱动器转换速率校准系统。实施例包括通过第一相位旋转器产生第一时钟信号; 由第二相位旋转器产生第二时钟信号; 由校准控制器初始设定相位选择器的数量，使得第一时钟信号相对于第二时钟信号被延迟; 确定所述第一时钟信号是否相对于所述第二时钟信号被延迟; 如果第一时钟信号被延迟，则改变第二相位选择器量; 并且如果所述第一时钟信号未被延迟，则使用所述第一时钟信号和所述第二时钟信号来校准被提供以控制校准时钟延迟线的转换速率的控制信号的值，使得所述校准时钟延迟线的转换速率基本上匹配目标转换速率。

7. 发明公开

US20240154620A1 TIME DOMAIN INTERLEAVING 审中-公开
公开(公告)号：US20240154620A1
公开(公告)日：2024-05-09
申请号：US18053940
申请日：2022-11-09
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Abdullah Serdar Yonar , Pier Andrea Francese , Marcel A. Kossel , Mridula Prathapan , Matthias Braendli , Thomas Morf
IPC分类号： H03M1/50
CPC分类号： H03M1/50
摘要： The invention is notably directed to a voltage-to-time converter comprising a first interleaving stage configured to perform a sampling of an input voltage, thereby generating a first set of sampled voltage signals. The first interleaving stage is further configured to perform a first voltage-to-time conversion in an interleaved manner, thereby generating a first set of time-interleaved signals in the time domain. A second interleaving stage is configured to perform a time-to-voltage conversion of the first set of time-interleaved signals, thereby generating a second set of sampled voltage signals. The second interleaving stage is further configured perform a second voltage-to-time conversion in an interleaved manner, thereby generating a second set of time-interleaved signals in the time domain.
The invention further concerns a related design structure and a related method.

8. 发明公开

US20230376736A1 NEURON CIRCUITS FOR SPIKING NEURAL NETWORKS 审中-公开
公开(公告)号：US20230376736A1
公开(公告)日：2023-11-23
申请号：US17664432
申请日：2022-05-23
申请人： International Business Machines Corporation
发明人： Giovanni Cherubini , Marcel A. Kossel
IPC分类号： G06N3/04 , G06N3/08 , G06F7/503
CPC分类号： G06N3/049 , G06N3/082 , G06F7/503
摘要： Neuron circuits are provided for spiking neural network apparatus having multiple such neuron circuits interconnected by links, each associated with a respective weight, for transmission of signals between neuron circuits. A neuron circuit includes a digital transmitter for generating trigger signals, indicating a state of the neuron circuit, on outgoing links of the circuit. The state is encoded in a time interval defined by these trigger signals. The neuron circuit includes a digital receiver for detecting such trigger signals on incoming links of the circuit, and digital accumulator logic. In response to detecting a trigger signal on an incoming link, the digital accumulator logic is adapted to generate a weighted signal dependent on the time interval and to accumulate the weighted signals generated from trigger signals on the incoming links to determine the state of the neuron circuit.

9. 发明申请

US20220407532A1 SUCCESSIVE-APPROXIMATION ANALOG-TO-DIGITAL CONVERTERS 有权
公开(公告)号：US20220407532A1
公开(公告)日：2022-12-22
申请号：US17354421
申请日：2021-06-22
申请人： International Business Machines Corporation
发明人： Abdullah Serdar Yonar , Pier Andrea Francese , Marcel A. Kossel
IPC分类号： H03M1/12 , H03M1/46 , H03M1/10
摘要： A successive-approximation analog-to-digital converter includes a sampling circuit for sampling an analog input signal to acquire a sampled voltage, and a regenerative comparator for comparing the sampled voltage with a succession of reference voltages to generate, for each reference voltage, a decision bit indicating the comparison result. The converter also includes a digital-to-analog converter which is adapted to generate the succession of reference voltages, in dependence on successive comparison results in the comparator, to progressively approximate the sampled voltage. The regenerative comparator comprises an integration circuit for generating output signals defining the decision bits, and a plurality of regeneration circuits for receiving these output signals. The regeneration circuits are operable, in response to respective control signals, to store respective decision bits defined by successive output signals from the integration circuit.

10. 发明授权

US11057039B1 Clock divider with quadrature error correction 有权
公开(公告)号：US11057039B1
公开(公告)日：2021-07-06
申请号：US16949325
申请日：2020-10-26
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Marcel A. Kossel , Vishal Khatri , Pier Andrea Francese , Matthias Braendli
IPC分类号： H03K21/40 , H03K21/02 , H03K21/10 , H04B1/40 , H03K23/44 , H03K3/037 , H03K5/156 , H04L27/36
摘要： The present disclosure relates to a method for quadrature error correction using a frequency divider circuit. The method comprises delaying input of data to master input terminals and/or slave input terminals of the frequency divider circuit for correcting a quadrature error between the in-phase and quadrature-phase output signals.

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