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1. 发明授权

US09990458B2 Generic design rule checking (DRC) test case extraction 有权
公开(公告)号：US09990458B2
公开(公告)日：2018-06-05
申请号：US15045696
申请日：2016-02-17
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Davinder Aggarwal , Vaibhav A. Ruparelia , Neha Singh , Janakiraman Viraraghavan
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A computer-aided testing is provided for design verification of integrated circuits. More specifically, a method of generating a test case in design rule checking is provided for that includes extracting coordinates of an error marker for a first error identified in an integrated circuit design. The method further includes identifying a first rectangle that encloses the error marker. The method further includes generating a first test case based on data of the integrated circuit design contained within the rectangle. The method further includes determining whether the first test case is representative of the first error. The method further includes in response to determining the first test case is not representative of the first error, identifying a second rectangle that is between the first rectangle and a third rectangle. The method further includes generating a second test case based on data of the integrated circuit design contained within the second rectangle.

2. 发明授权

US08875064B2 Automated design rule checking (DRC) test case generation 有权
标题翻译：自动设计规则检查（DRC）测试用例生成
公开(公告)号：US08875064B2
公开(公告)日：2014-10-28
申请号：US13833028
申请日：2013-03-15
申请人： International Business Machines Corporation
发明人： Davinder Aggarwal , Vibhor Jain , Janakiraman Viraraghavan
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Approaches for generating test cases for design rule checking are provided. A method includes extracting coordinates of an error marker in an integrated circuit design. The method also includes creating an error polygon using the coordinates. The method additionally includes selecting polygons in the design that touch the error polygon. The method further includes identifying a rectangle that encloses the selected polygons. The method also includes generating a test case based on data of the design contained within the rectangle. The extracting, the creating, the selecting, the identifying, and the generating are performed using a computer device.
摘要翻译：提供了用于生成设计规则检查的测试用例的方法。一种方法包括在集成电路设计中提取错误标记的坐标。该方法还包括使用坐标创建错误多边形。该方法还包括在设计中选择触摸误差多边形的多边形。该方法还包括识别包围所选择的多边形的矩形。该方法还包括基于包含在矩形内的设计的数据生成测试用例。使用计算机设备执行提取，创建，选择，识别和生成。

3. 发明授权

US09292652B2 Generic design rule checking (DRC) test case extraction 有权
标题翻译：通用设计规则检查（DRC）测试用例提取
公开(公告)号：US09292652B2
公开(公告)日：2016-03-22
申请号：US14270528
申请日：2014-05-06
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Davinder Aggarwal , Vaibhav A. Ruparelia , Neha Singh , Janakiraman Viraraghavan
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5081
摘要： A computer-aided testing is provided for design verification of integrated circuits. More specifically, a method of generating a test case in design rule checking is provided for that includes extracting coordinates of an error marker for a first error identified in an integrated circuit design. The method further includes identifying a first rectangle that encloses the error marker. The method further includes generating a first test case based on data of the integrated circuit design contained within the rectangle. The method further includes determining whether the first test case is representative of the first error. The method further includes in response to determining the first test case is not representative of the first error, identifying a second rectangle that is between the first rectangle and a third rectangle. The method further includes generating a second test case based on data of the integrated circuit design contained within the second rectangle.
摘要翻译：为集成电路的设计验证提供了计算机辅助测试。更具体地，提供了一种在设计规则检查中生成测试用例的方法，其包括提取在集成电路设计中识别的第一错误的错误标记的坐标。该方法还包括识别包围误差标记的第一矩形。该方法还包括基于包含在矩形内的集成电路设计的数据来生成第一测试用例。该方法还包括确定第一测试用例是否代表第一错误。该方法还包括响应于确定第一测试用例不代表第一错误，识别第一矩形和第三矩形之间的第二矩形。该方法还包括基于包含在第二矩形内的集成电路设计的数据生成第二测试用例。

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