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1. 发明授权

US10804368B2 Semiconductor device having two-part spacer 有权
公开(公告)号：US10804368B2
公开(公告)日：2020-10-13
申请号：US16049403
申请日：2018-07-30
申请人： International Business Machines Corporation
发明人： Ruqiang Bao , Junli Wang , Dechao Guo , Heng Wu , Ernest Y. Wu
IPC分类号： H01L29/51 , H01L29/78 , H01L29/66 , H01L29/417
摘要： Techniques for fabricating a semiconductor device having a two-part spacer. In one embodiment, a device is provided that comprises a spacer having a first portion and a second portion, where the first portion comprises one or more layers and the second portion comprises a dielectric material. In one or more implementations, the device further comprises an isolation layer coupled to the spacer, where the isolation layer comprises a silicon oxide material. In one or implementation, the device can further comprise a gate structure formed on a substrate, where the gate structure comprises a polysilicon contact portion, a first silicon dioxide portion, a silicon nitride portion and a second silicon dioxide portion.

2. 发明授权

US10770393B2 BEOL thin film resistor 有权
公开(公告)号：US10770393B2
公开(公告)日：2020-09-08
申请号：US15925835
申请日：2018-03-20
申请人： International Business Machines Corporation
发明人： Andrew Tae Kim , Baozhen Li , Ernest Y. Wu , Chih-Chao Yang
IPC分类号： H01L29/00 , H01L23/522 , H01L23/525 , H01L27/01 , H01L21/768 , H01L23/532
摘要： Back end of the line precision resistors that allow for high currents and for configuration as an eFuse by embedding a single thin film high resistive metal material within a dielectric layer, wherein the resisters are coupled to sidewalls of adjacent metal interconnects are described. The resistors can be formed in the metal one (M1) dielectric layer and can be coupled to sidewalls of the M1 interconnects. Also described are processes for fabricating integrated circuits including the resistors and/or e-Fuses.

3. 发明授权

US10651083B2 Graded interconnect cap 有权
公开(公告)号：US10651083B2
公开(公告)日：2020-05-12
申请号：US15911313
申请日：2018-03-05
申请人： International Business Machines Corporation
发明人： Andrew Tae Kim , Baozhen Li , Ernest Y. Wu , Chih-Chao Yang
IPC分类号： H01L23/52 , H01L21/768 , H01L23/532
摘要： A graded cap is formed upon an interconnect, such as a back end of line wire. The graded cap includes a microstructure that uniformly changes from a metal nearest the interconnect to a metal nitride most distal from the interconnect. The graded cap is formed by nitriding a metal cap that is formed upon the interconnect. During nitriding an exposed one or more perimeter portions of the metal cap become a metal nitride with a larger amount or concentration of Nitrogen while one or more inner portions of the metal cap nearest the interconnect may be maintained as the metal or become the metal nitride with a fewer amount or concentration of Nitrogen. The resulting graded cap includes a gradually or uniformly changing microstructure between the one or more inner portions and the one or more perimeter portions.

4. 发明申请

US20200035808A1 SEMICONDUCTOR DEVICE HAVING TWO-PART SPACER 审中-公开
公开(公告)号：US20200035808A1
公开(公告)日：2020-01-30
申请号：US16049403
申请日：2018-07-30
申请人： International Business Machines Corporation
发明人： Ruqiang Bao , Junli Wang , Dechao Guo , Heng Wu , Ernest Y. Wu
IPC分类号： H01L29/51 , H01L29/78 , H01L29/417 , H01L29/66
摘要： Techniques for fabricating a semiconductor device having a two-part spacer. In one embodiment, a device is provided that comprises a spacer having a first portion and a second portion, where the first portion comprises one or more layers and the second portion comprises a dielectric material. In one or more implementations, the device further comprises an isolation layer coupled to the spacer, where the isolation layer comprises a silicon oxide material. In one or implementation, the device can further comprise a gate structure formed on a substrate, where the gate structure comprises a polysilicon contact portion, a first silicon dioxide portion, a silicon nitride portion and a second silicon dioxide portion.

5. 发明申请

US20180074114A1 OPTIMIZATION OF INTEGRATED CIRCUIT RELIABILITY 审中-公开
公开(公告)号：US20180074114A1
公开(公告)日：2018-03-15
申请号：US15814658
申请日：2017-11-16
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Carole D. Graas , Nazmul Habib , Deborah M. Massey , John G. Massey , Pascal A. Nsame , Ernest Y. Wu , Emmanuel Yashchin
IPC分类号： G01R31/26 , G01R31/02 , G01R31/28
CPC分类号： G01R31/26 , G01R31/025 , G01R31/2856 , Y02T10/82
摘要： A per-chip equivalent oxide thickness (EOT) circuit sensor resides in an integrated circuit. The per-chip EOT circuit sensor determines electrical characteristics of the integrated circuit. The measured electrical characteristics include leakage current. The determined electrical characteristics are used to determine physical attributes of the integrated circuit. The physical attributes, including EOT, are used in a reliability model to predict per-chip failure rate.

6. 发明申请

US20170285094A1 OPTIMIZATION OF INTEGRATED CIRCUIT RELIABILITY 审中-公开
公开(公告)号：US20170285094A1
公开(公告)日：2017-10-05
申请号：US15630415
申请日：2017-06-22
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Carole D. Graas , Nazmul Habib , Deborah M. Massey , John G. Massey , Pascal A. Nsame , Ernest Y. Wu , Emmanuel Yashchin
IPC分类号： G01R31/26 , G01R31/02 , G01R31/28
CPC分类号： G01R31/26 , G01R31/025 , G01R31/2856 , Y02T10/82
摘要： A per-chip equivalent oxide thickness (EOT) circuit sensor resides in an integrated circuit. The per-chip EOT circuit sensor determines electrical characteristics of the integrated circuit. The measured electrical characteristics include leakage current. The determined electrical characteristics are used to determine physical attributes of the integrated circuit. The physical attributes, including EOT, are used in a reliability model to predict per-chip failure rate.

7. 发明申请

US20140195175A1 MEASURING DIELECTRIC BREAKDOWN IN A DYNAMIC MODE 审中-公开
标题翻译：以动态模式测量电介质断开
公开(公告)号：US20140195175A1
公开(公告)日：2014-07-10
申请号：US13734075
申请日：2013-01-04
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Eduard A. Cartier , Charles LaRow , Travis S. Merrill , Ernest Y. Wu
IPC分类号： G01R31/14 , G06F17/10
CPC分类号： G06F17/10 , G01R31/129 , G01R31/3008
摘要： Embodiments of the present invention provide a method, system, and program product for testing a semiconductor device to measure dielectric breakdown. A computer applies a plurality of stress voltages to a semiconductor device under test. The computer determines a plurality of current measurements until a failure criteria occurs, using a predefined voltage ramp rate and a predefined plurality of stress voltage steps, wherein the number of the plurality of current measurements is less than or equal to the number of the predefined plurality of voltage steps. The computer identifies a stress voltage at which the semiconductor device fails. The computer calculates a frequency dependent voltage acceleration factor based on the quotient of the natural log of the voltage at which the semiconductor device under test failed to the natural log of the predetermined voltage ramp rate.
摘要翻译：本发明的实施例提供了一种用于测试半导体器件以测量电介质击穿的方法，系统和程序产品。计算机对被测半导体器件施加多个应力电压。计算机使用预定义的电压斜坡率和预定义的多个应力电压步骤来确定多个电流测量直到发生故障标准，其中多个电流测量的数量小于或等于预定义多个的数量的电压步进。计算机识别半导体器件失效的应力电压。计算机根据被测半导体器件的电压的自然对数的商与预定电压斜坡率的自然对数计算频率相关的电压加速因子。

8. 发明授权

US11257750B2 E-fuse co-processed with MIM capacitor 有权
公开(公告)号：US11257750B2
公开(公告)日：2022-02-22
申请号：US16783812
申请日：2020-02-06
申请人： International Business Machines Corporation
发明人： Baozhen Li , Chih-Chao Yang , Jim Shih-Chun Liang , Ernest Y. Wu
IPC分类号： H01L23/522 , H01L23/525 , H01L23/528 , H01L49/02
摘要： Metal e-fuse structure formed during back-end-of-line during processing and integral with on-chip metal-insulator-metal (MIM) capacitor (MIMcap). The metal e-fuse structures are extensions of MIMcap electrodes and are structured to isolate BEOL MIM capacitors for trimming and/or to isolate shorted or rendered highly leaky due to in process, or service induced defects. In one embodiment, the method incorporates the integral, co-processed metal e-fuse in series between the MIM capacitor and an active circuit. When a high current passes through the e-fuse element, the e-fuse element is rendered highly resistive or electrically open thereby disconnecting the MIM capacitor or electrode plate from the active circuitry. The e-fuse structure may comprise a thin neck portion(s) or zig-zag neck portion that extend from an MIMcap electrode away from the MIMcap between two inter-level interconnect via structures.

9. 发明申请

US20210249348A1 E-FUSE CO-PROCESSED WITH MIM CAPACITOR 有权
公开(公告)号：US20210249348A1
公开(公告)日：2021-08-12
申请号：US16783812
申请日：2020-02-06
申请人： International Business Machines Corporation
发明人： Baozhen Li , Chih-Chao Yang , JIM SHIH-CHUN LIANG , Ernest Y. Wu
IPC分类号： H01L23/522 , H01L49/02 , H01L23/528 , H01L23/525
摘要： Metal e-fuse structure formed during back-end-of-line during processing and integral with on-chip metal-insulator-metal (MIM) capacitor (MIMcap). The metal e-fuse structures are extensions of MIMcap electrodes and are structured to isolate BEOL MIM capacitors for trimming and/or to isolate shorted or rendered highly leaky due to in process, or service induced defects. In one embodiment, the method incorporates the integral, co-processed metal e-fuse in series between the MIM capacitor and an active circuit. When a high current passes through the e-fuse element, the e-fuse element is rendered highly resistive or electrically open thereby disconnecting the MIM capacitor or electrode plate from the active circuitry. The e-fuse structure may comprise a thin neck portion(s) or zig-zag neck portion that extend from an MIMcap electrode away from the MIMcap between two inter-level interconnect via structures.

10. 发明授权

US10989754B2 Optimization of integrated circuit reliability 有权
公开(公告)号：US10989754B2
公开(公告)日：2021-04-27
申请号：US15814658
申请日：2017-11-16
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Carole D. Graas , Nazmul Habib , Deborah M. Massey , John G. Massey , Pascal A. Nsame , Ernest Y. Wu , Emmanuel Yashchin
IPC分类号： G01R31/26 , G01R31/28 , G01R31/50
摘要： A per-chip equivalent oxide thickness (EOT) circuit sensor resides in an integrated circuit. The per-chip EOT circuit sensor determines electrical characteristics of the integrated circuit. The measured electrical characteristics include leakage current. The determined electrical characteristics are used to determine physical attributes of the integrated circuit. The physical attributes, including EOT, are used in a reliability model to predict per-chip failure rate.

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