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1. 发明申请

US20160011996A1 MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER 有权
标题翻译：多层高效平行超级计算机
公开(公告)号：US20160011996A1
公开(公告)日：2016-01-14
申请号：US14701371
申请日：2015-04-30
申请人： International Business Machines Corporation
发明人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
IPC分类号： G06F13/28 , G06F9/38 , G06F9/30 , G06F15/80 , G06F12/08
CPC分类号： G06F13/287 , G06F9/06 , G06F9/3004 , G06F9/30047 , G06F9/3885 , G06F12/0811 , G06F12/0831 , G06F12/0862 , G06F12/0864 , G06F12/1027 , G06F15/17381 , G06F15/17387 , G06F15/76 , G06F15/8069 , G06F2212/1016 , G06F2212/602 , G06F2212/6022 , G06F2212/6024 , G06F2212/6032 , Y02D10/13 , Y02D10/14
摘要： A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.
摘要翻译： 100 petaflop规模的多千兆高效并行超级计算机包括基于片上系统技术的节点架构，其中每个处理节点包括单个专用集成电路（ASIC）。 ASIC节点通过五维环面网络互连，最优化节点之间的分组通信的吞吐量并最小化等待时间。网络实现集体网络和提供全局障碍和通知功能的全球异步网络。集成在节点设计中包括一个基于列表的预取器。存储系统实现事务存储器，线程级别推测和多重切换缓存，同时提高软错误率，并支持DMA功能，允许并行处理消息传递。

2. 发明授权

US09223729B2 Servicing a globally broadcast interrupt signal in a multi-threaded computer 有权
标题翻译：在多线程计算机中维护全局广播中断信号
公开(公告)号：US09223729B2
公开(公告)日：2015-12-29
申请号：US13804223
申请日：2013-03-14
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： John E. Attinella , Kristan D. Davis , Roy G. Musselman , David L. Satterfield
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： Methods, apparatuses, and computer program products for servicing a globally broadcast interrupt signal in a multi-threaded computer comprising a plurality of processor threads. Embodiments include an interrupt controller indicating in a plurality of local interrupt status locations that a globally broadcast interrupt signal has been received by the interrupt controller. Embodiments also include a thread determining that a local interrupt status location corresponding to the thread indicates that the globally broadcast interrupt signal has been received by the interrupt controller. Embodiments also include the thread processing one or more entries in a global interrupt status bit queue based on whether global interrupt status bits associated with the globally broadcast interrupt signal are locked. Each entry in the global interrupt status bit queue corresponds to a queued global interrupt.
摘要翻译：用于在包括多个处理器线程的多线程计算机中服务于全球广播中断信号的方法，装置和计算机程序产品。实施例包括在多个局部中断状态位置中指示全局广播中断信号已被中断控制器接收的中断控制器。实施例还包括线程，确定对应于线程的本地中断状态位置指示全局广播中断信号已被中断控制器接收。实施例还包括基于与全局广播中断信号相关联的全局中断状态位被锁定的线程处理全局中断状态位队列中的一个或多个条目。全局中断状态位队列中的每个条目对应于排队的全局中断。

3. 发明授权

US10713043B2 Opcode counting for performance measurement 有权
公开(公告)号：US10713043B2
公开(公告)日：2020-07-14
申请号：US15918363
申请日：2018-03-12
申请人： International Business Machines Corporation
发明人： Alan Gara , David L. Satterfield , Robert E. Walkup
IPC分类号： G06F9/30 , G06F11/34 , G06F11/30 , G06F15/173 , H04L29/08
摘要： Methods, systems and computer program products are disclosed for measuring a performance of a program running on a processing unit of a processing system. In one embodiment, the method comprises informing a logic unit of each instruction in the program that is executed by the processing unit, assigning a weight to each instruction, assigning the instructions to a plurality of groups, and analyzing the plurality of groups to measure one or more metrics. In one embodiment, each instruction includes an operating code portion, and the assigning includes assigning the instructions to the groups based on the operating code portions of the instructions. In an embodiment, each type of instruction is assigned to a respective one of the plurality of groups. These groups may be combined into a plurality of sets of the groups.

4. 发明申请

US20180203693A1 OPCODE COUNTING FOR PERFORMANCE MEASUREMENT 审中-公开
公开(公告)号：US20180203693A1
公开(公告)日：2018-07-19
申请号：US15918363
申请日：2018-03-12
申请人： International Business Machines Corporation
发明人： Alan Gara , David L. Satterfield , Robert E. Walkup
IPC分类号： G06F9/30 , H04L29/08 , G06F11/34 , G06F15/173 , G06F11/30
CPC分类号： G06F9/30021 , G06F9/3001 , G06F9/30018 , G06F9/30145 , G06F11/3024 , G06F11/3409 , G06F11/348 , G06F15/17362 , G06F15/17381 , G06F15/17393 , G06F2201/88 , H04L67/10
摘要： Methods, systems and computer program products are disclosed for measuring a performance of a program running on a processing unit of a processing system. In one embodiment, the method comprises informing a logic unit of each instruction in the program that is executed by the processing unit, assigning a weight to each instruction, assigning the instructions to a plurality of groups, and analyzing the plurality of groups to measure one or more metrics. In one embodiment, each instruction includes an operating code portion, and the assigning includes assigning the instructions to the groups based on the operating code portions of the instructions. In an embodiment, each type of instruction is assigned to a respective one of the plurality of groups. These groups may be combined into a plurality of sets of the groups.

5. 发明授权

US09921831B2 Opcode counting for performance measurement 有权
公开(公告)号：US09921831B2
公开(公告)日：2018-03-20
申请号：US15291351
申请日：2016-10-12
申请人： International Business Machines Corporation
发明人： Alan Gara , David L. Satterfield , Robert E. Walkup
IPC分类号： G06F9/30 , G06F11/34 , G06F11/30 , G06F15/173 , H04L29/08
CPC分类号： G06F9/30021 , G06F9/3001 , G06F9/30018 , G06F9/30145 , G06F11/3024 , G06F11/3409 , G06F11/348 , G06F15/17362 , G06F15/17381 , G06F15/17393 , G06F2201/88 , H04L67/10
摘要： Methods, systems and computer program products are disclosed for measuring a performance of a program running on a processing unit of a processing system. In one embodiment, the method comprises informing a logic unit of each instruction in the program that is executed by the processing unit, assigning a weight to each instruction, assigning the instructions to a plurality of groups, and analyzing the plurality of groups to measure one or more metrics. In one embodiment, each instruction includes an operating code portion, and the assigning includes assigning the instructions to the groups based on the operating code portions of the instructions. In an embodiment, each type of instruction is assigned to a respective one of the plurality of groups. These groups may be combined into a plurality of sets of the groups.

6. 发明授权

US09473569B2 Opcode counting for performance measurement 有权
公开(公告)号：US09473569B2
公开(公告)日：2016-10-18
申请号：US14800311
申请日：2015-07-15
申请人： International Business Machines Corporation
发明人： Alan Gara , David L. Satterfield , Robert E. Walkup
IPC分类号： G06F15/00 , H04L29/08 , G06F11/34 , G06F11/30 , G06F15/173 , G06F9/30
CPC分类号： G06F9/30021 , G06F9/3001 , G06F9/30018 , G06F9/30145 , G06F11/3024 , G06F11/3409 , G06F11/348 , G06F15/17362 , G06F15/17381 , G06F15/17393 , G06F2201/88 , H04L67/10
摘要： Methods, systems and computer program products are disclosed for measuring a performance of a program running on a processing unit of a processing system. In one embodiment, the method comprises informing a logic unit of each instruction in the program that is executed by the processing unit, assigning a weight to each instruction, assigning the instructions to a plurality of groups, and analyzing the plurality of groups to measure one or more metrics. In one embodiment, each instruction includes an operating code portion, and the assigning includes assigning the instructions to the groups based on the operating code portions of the instructions. In an embodiment, each type of instruction is assigned to a respective one of the plurality of groups. These groups may be combined into a plurality of sets of the groups.

7. 发明申请

US20140281089A1 Servicing A Globally Broadcast Interrupt Signal In A Multi-Threaded Computer 有权
标题翻译：在多线程计算机中维护全局广播中断信号
公开(公告)号：US20140281089A1
公开(公告)日：2014-09-18
申请号：US13795019
申请日：2013-03-12
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： John E. Attinella , Kristan D. Davis , Roy G. Musselman , David L. Satterfield
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： Methods, apparatuses, and computer program products for servicing a globally broadcast interrupt signal in a multi-threaded computer comprising a plurality of processor threads. Embodiments include an interrupt controller indicating in a plurality of local interrupt status locations that a globally broadcast interrupt signal has been received by the interrupt controller. Embodiments also include a thread determining that a local interrupt status location corresponding to the thread indicates that the globally broadcast interrupt signal has been received by the interrupt controller. Embodiments also include the thread processing one or more entries in a global interrupt status bit queue based on whether global interrupt status bits associated with the globally broadcast interrupt signal are locked. Each entry in the global interrupt status bit queue corresponds to a queued global interrupt.
摘要翻译：用于在包括多个处理器线程的多线程计算机中服务于全球广播中断信号的方法，装置和计算机程序产品。实施例包括在多个局部中断状态位置中指示全局广播中断信号已被中断控制器接收的中断控制器。实施例还包括线程，确定对应于线程的本地中断状态位置指示全局广播中断信号已被中断控制器接收。实施例还包括基于与全局广播中断信号相关联的全局中断状态位被锁定的线程处理全局中断状态位队列中的一个或多个条目。全局中断状态位队列中的每个条目对应于排队的全局中断。

8. 发明申请

US20140052970A1 OPCODE COUNTING FOR PERFORMANCE MEASUREMENT 有权
标题翻译：用于性能测量的操作码计数
公开(公告)号：US20140052970A1
公开(公告)日：2014-02-20
申请号：US14063610
申请日：2013-10-25
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Alan Gara , David L. Satterfield , Robert E. Walkup
IPC分类号： G06F9/30
CPC分类号： G06F9/30021 , G06F9/3001 , G06F9/30018 , G06F9/30145 , G06F11/3024 , G06F11/3409 , G06F11/348 , G06F15/17362 , G06F15/17381 , G06F15/17393 , G06F2201/88 , H04L67/10
摘要： Methods, systems and computer program products are disclosed for measuring a performance of a program running on a processing unit of a processing system. In one embodiment, the method comprises informing a logic unit of each instruction in the program that is executed by the processing unit, assigning a weight to each instruction, assigning the instructions to a plurality of groups, and analyzing the plurality of groups to measure one or more metrics. In one embodiment, each instruction includes an operating code portion, and the assigning includes assigning the instructions to the groups based on the operating code portions of the instructions. In an embodiment, each type of instruction is assigned to a respective one of the plurality of groups. These groups may be combined into a plurality of sets of the groups.
摘要翻译：公开了用于测量在处理系统的处理单元上运行的程序的性能的方法，系统和计算机程序产品。在一个实施例中，该方法包括通知处理单元执行的程序中的每个指令的逻辑单元，向每个指令分配权重，将指令分配给多个组，以及分析多个组以测量一个或更多指标。在一个实施例中，每个指令包括操作代码部分，并且分配包括基于指令的操作代码部分将指令分配给组。在一个实施例中，每种类型的指令被分配给多个组中的相应一个。这些组可以组合成多个组的组。

9. 发明申请

US20170068536A1 OPCODE COUNTING FOR PERFORMANCE MEASUREMENT 有权
标题翻译：用于性能测量的操作码计数
公开(公告)号：US20170068536A1
公开(公告)日：2017-03-09
申请号：US15291351
申请日：2016-10-12
申请人： International Business Machines Corporation
发明人： Alan Gara , David L. Satterfield , Robert E. Walkup
IPC分类号： G06F9/30
CPC分类号： G06F9/30021 , G06F9/3001 , G06F9/30018 , G06F9/30145 , G06F11/3024 , G06F11/3409 , G06F11/348 , G06F15/17362 , G06F15/17381 , G06F15/17393 , G06F2201/88 , H04L67/10
摘要： Methods, systems and computer program products are disclosed for measuring a performance of a program running on a processing unit of a processing system. In one embodiment, the method comprises informing a logic unit of each instruction in the program that is executed by the processing unit, assigning a weight to each instruction, assigning the instructions to a plurality of groups, and analyzing the plurality of groups to measure one or more metrics. In one embodiment, each instruction includes an operating code portion, and the assigning includes assigning the instructions to the groups based on the operating code portions of the instructions. In an embodiment, each type of instruction is assigned to a respective one of the plurality of groups. These groups may be combined into a plurality of sets of the groups.
摘要翻译：公开了用于测量在处理系统的处理单元上运行的程序的性能的方法，系统和计算机程序产品。在一个实施例中，该方法包括通知处理单元执行的程序中的每个指令的逻辑单元，向每个指令分配权重，将指令分配给多个组，以及分析多个组以测量一个或更多指标。在一个实施例中，每个指令包括操作代码部分，并且分配包括基于指令的操作代码部分将指令分配给组。在一个实施例中，每种类型的指令被分配给多个组中的相应一个组。这些组可以组合成多个组的组。

10. 发明授权

US09223728B2 Servicing a globally broadcast interrupt signal in a multi-threaded computer 有权
公开(公告)号：US09223728B2
公开(公告)日：2015-12-29
申请号：US13795019
申请日：2013-03-12
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： John E. Attinella , Kristan D. Davis , Roy G. Musselman , David L. Satterfield
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： Methods, apparatuses, and computer program products for servicing a globally broadcast interrupt signal in a multi-threaded computer comprising a plurality of processor threads. Embodiments include an interrupt controller indicating in a plurality of local interrupt status locations that a globally broadcast interrupt signal has been received by the interrupt controller. Embodiments also include a thread determining that a local interrupt status location corresponding to the thread indicates that the globally broadcast interrupt signal has been received by the interrupt controller. Embodiments also include the thread processing one or more entries in a global interrupt status bit queue based on whether global interrupt status bits associated with the globally broadcast interrupt signal are locked. Each entry in the global interrupt status bit queue corresponds to a queued global interrupt.

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