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1. 发明申请

US20170200620A1 IMPLANT AFTER THROUGH-SILICON VIA (TSV) ETCH TO GETTER MOBILE IONS 审中-公开
公开(公告)号：US20170200620A1
公开(公告)日：2017-07-13
申请号：US14994598
申请日：2016-01-13
申请人： International Business Machines Corporation
发明人： Christopher Collins , Mukta G. Farooq , Troy L. Graves-Abe , Brian J. Greene , Robert Hannon , Herbert L. Ho , Chandrasekharan Kothandaraman
IPC分类号： H01L21/322 , H01L21/308 , H01L23/532 , H01L23/522 , H01L23/528 , H01L21/768 , H01L29/167
CPC分类号： H01L21/3226 , H01L21/26586 , H01L21/308 , H01L21/743 , H01L21/76879 , H01L21/76898 , H01L23/5226 , H01L23/528 , H01L23/53214 , H01L23/53228 , H01L23/53257 , H01L29/167
摘要： A method of making a semiconductor device includes disposing a mask on a substrate; etching the mask to form an opening in the mask; etching a trench in the substrate beneath the opening in the mask; and implanting a dopant in an area of the substrate beneath the opening of the mask, the dopant capable of gettering mobile ions that can contaminate the substrate; wherein the dopant extends through the substrate from a sidewall of the trench and an endwall of the trench.

2. 发明授权

US09443854B2 FinFET with constrained source-drain epitaxial region 有权
标题翻译：具有约束源极 - 漏极外延区域的FinFET
公开(公告)号：US09443854B2
公开(公告)日：2016-09-13
申请号：US14920938
申请日：2015-10-23
申请人： International Business Machines Corporation
发明人： Brian J. Greene , Arvind Kumar , Dan M. Mocuta
IPC分类号： H01L27/088 , H01L21/8234 , H01L29/66 , H01L29/78 , H01L29/165 , H01L21/3105 , H01L29/04 , H01L21/84
CPC分类号： H01L27/0886 , H01L21/31053 , H01L21/823418 , H01L21/823431 , H01L21/823437 , H01L21/823468 , H01L21/823814 , H01L21/823821 , H01L21/845 , H01L27/0924 , H01L29/045 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/6656 , H01L29/66636 , H01L29/7848 , H01L29/7853
摘要： A method includes forming a plurality of fins on a substrate, conformally depositing a nitride liner above and in direct contact with the plurality of fins and the substrate, removing a top portion of the nitride liner above the plurality of fins to expose a top surface of the plurality of fins, forming a gate over a first portion of the plurality of fins, a second portion of the plurality of fins remains exposed, forming spacers on opposite sidewalls of the nitride liner on the second portion of the plurality of fins, removing the second portion of the plurality of fins to form a trench between opposing sidewalls of the nitride liner, and forming an epitaxial layer in the trench, the lateral growth of the epitaxial layer is constrained by the nitride liner to form constrained source-drain regions.
摘要翻译：一种方法包括在衬底上形成多个散热片，在氮化物衬垫的上方并与多个翅片和衬底直接接触地共形沉积氮化物衬垫，去除多个翅片之上的氮化物衬垫的顶部以暴露出顶部表面所述多个散热片在所述多个散热片的第一部分上形成栅极，所述多个散热片的第二部分保持暴露，在所述多个散热片的第二部分上的所述氮化物衬垫的相对侧壁上形成隔离物，多个翅片的第二部分以在氮化物衬垫的相对侧壁之间形成沟槽，并且在沟槽中形成外延层，外延层的横向生长由氮化物衬垫约束以形成受限的源极 - 漏极区域。

3. 发明申请

US20150357412A1 CONSTRAINED EPITAXIAL SOURCE/DRAIN REGIONS ON SEMICONDUCTOR-ON-INSULATOR FINFET DEVICE 有权
标题翻译：半导体绝缘体FINFET器件的约束外延源/漏极区
公开(公告)号：US20150357412A1
公开(公告)日：2015-12-10
申请号：US14827535
申请日：2015-08-17
申请人： International Business Machines Corporation
发明人： Brian J. Greene , Arvind Kumar , Dan M. Mocuta
IPC分类号： H01L29/08 , H01L29/165 , H01L29/16 , H01L29/78 , H01L29/06
CPC分类号： H01L29/0847 , H01L29/0653 , H01L29/16 , H01L29/165 , H01L29/66545 , H01L29/66795 , H01L29/6681 , H01L29/785
摘要： A method of fabricating a semiconductor device includes forming a plurality of semiconductor fins on an insulator layer of a semiconductor substrate, and forming a plurality of gate stacks on the insulator layer. Each gate stack wraps around a respective portion of the semiconductor fins. The method further includes forming a dielectric layer on the insulator layer. The dielectric layer fills voids between the semiconductor fins and gate stacks, and covers the semiconductor fins. The method further includes etching at least one portion of the semiconductor fins until reaching the insulator layer such that at least one cavity is formed. The cavity exposes seed regions of the semiconductor fins located between adjacent gate stacks. The method further includes epitaxially growing a semiconductor material from the seed regions to form source/drain regions corresponding to a respective gate stack.
摘要翻译：制造半导体器件的方法包括在半导体衬底的绝缘体层上形成多个半导体鳍片，并在绝缘体层上形成多个栅叠层。每个栅极堆叠绕在半导体鳍片的相应部分周围。该方法还包括在绝缘体层上形成电介质层。电介质层填充半导体鳍片和栅极叠层之间的空隙，并覆盖半导体鳍片。该方法还包括蚀刻半导体鳍片的至少一部分直到到达绝缘体层，使得形成至少一个空腔。空腔暴露位于相邻栅极叠层之间的半导体鳍片的种子区域。该方法还包括从种子区域外延生长半导体材料以形成对应于相应栅极堆叠的源极/漏极区域。

4. 发明申请

US20150333145A1 HIGH DENSITY FINFET DEVICES WITH UNMERGED FINS 审中-公开
标题翻译：高密度FINFET器件与未知的FINS
公开(公告)号：US20150333145A1
公开(公告)日：2015-11-19
申请号：US14278674
申请日：2014-05-15
申请人： International Business Machines Corporation
发明人： Michael P. Chudzik , Brian J. Greene , Edward P. Maciejewski , Kevin McStay , Shreesh Narasimha , Chengwen Pei , Werner A. Rausch
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L29/66795 , H01L29/66545 , H01L29/6681 , H01L29/785
摘要： Embodiments of the present invention provide a finFET and method of fabrication to achieve advantages of both merged and unmerged fins. A first step of epitaxy is performed with either partial diamond or full diamond growth. This is followed by a second step of deposition of a semiconductor cap region on the finFET source/drain area using a directional deposition process, followed by an anneal to perform Solid Phase Epitaxy or poly recrystalization. As a result, the fins remain unmerged, but the epitaxial volume is increased to provide reduced contact resistance. Embodiments of the present invention allow a narrower fin pitch, which enables increased circuit density on an integrated circuit.
摘要翻译：本发明的实施例提供了finFET和制造方法，以实现合并和非鳍片翅片的优点。用部分金刚石或全金刚石生长进行外延的第一步。随后是使用定向沉积工艺在finFET源/漏区上沉积半导体盖区域，随后进行退火以进行固相外延或多重重结晶的第二步骤。结果，翅片保持未熔化，但外延体积增加以提供降低的接触电阻。本发明的实施例允许更窄的翅片间距，其能够增加集成电路上的电路密度。

5. 发明授权

US09105722B2 Tucked active region without dummy poly for performance boost and variation reduction 有权
标题翻译：带虚拟聚合物的带状活性区域用于性能提升和变异减少
公开(公告)号：US09105722B2
公开(公告)日：2015-08-11
申请号：US14486108
申请日：2014-09-15
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Brian J. Greene , Yue Liang , Xiaojun Yu
IPC分类号： H01L29/76 , H01L29/78 , H01L21/28 , H01L29/66 , H01L29/165 , H01L21/02 , H01L21/762 , H01L29/06
CPC分类号： H01L29/7848 , H01L21/02112 , H01L21/02532 , H01L21/28123 , H01L21/76224 , H01L29/0649 , H01L29/165 , H01L29/66545 , H01L29/66553 , H01L29/66568 , H01L29/66636
摘要： In one embodiment, a semiconductor device is provided that includes a semiconductor substrate including an active region and at least one trench isolation region at a perimeter of the active region, and a functional gate structure present on a portion of the active region of the semiconductor substrate. Embedded semiconductor regions are present in the active region of the semiconductor substrate on opposing sides of the portion of the active region that the functional gate structure is present on. A portion of the active region of the semiconductor substrate separates the outermost edge of the embedded semiconductor regions from the at least one isolation region. Methods of forming the aforementioned device are also provided.
摘要翻译：在一个实施例中，提供了半导体器件，其包括半导体衬底，该半导体衬底包括有源区和位于有源区的周边的至少一个沟槽隔离区，以及存在于半导体衬底的有源区的一部分上的功能栅结构。嵌入式半导体区域存在于半导体衬底的有源区域中，在有源区域的存在功能栅极结构的部分的相对侧上。半导体衬底的有源区域的一部分将嵌入的半导体区域的最外边缘与至少一个隔离区域分开。还提供了形成上述装置的方法。

6. 发明授权

US09093275B2 Multi-height multi-composition semiconductor fins 有权
标题翻译：多高度多组分半导体鳍片
公开(公告)号：US09093275B2
公开(公告)日：2015-07-28
申请号：US14059797
申请日：2013-10-22
申请人： International Business Machines Corporation
发明人： Brian J. Greene , Augustin J. Hong , Byeong Y. Kim , Dan M. Mocuta
IPC分类号： H01L21/027 , H01L21/02 , H01L29/78 , H01L29/786 , H01L21/18 , H01L29/165
CPC分类号： H01L27/1211 , H01L21/02433 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L21/02636 , H01L21/02639 , H01L21/182 , H01L21/845 , H01L29/04 , H01L29/1608 , H01L29/165 , H01L29/785 , H01L29/78603
摘要： A dielectric material layer is formed on a semiconductor-on-insulator (SOI) substrate including a top semiconductor layer containing a first semiconductor material. An opening is formed within the dielectric material layer, and a trench is formed in the top semiconductor layer within the area of the opening by an etch. A second semiconductor material is deposited to a height above the top surface of the top semiconductor layer employing a selective epitaxy process. Another dielectric material layer can be deposited, and another trench can be formed in the top semiconductor layer. Another semiconductor material can be deposited to a different height employing another selective epitaxy process. The various semiconductor material portions can be patterned to form semiconductor fins having different heights and/or different compositions.
摘要翻译：在包含第一半导体材料的顶部半导体层的绝缘体上半导体（SOI）基板上形成电介质材料层。在电介质材料层内形成一个开口，并通过蚀刻在开口区域内的顶部半导体层中形成沟槽。使用选择性外延工艺将第二半导体材料沉积到顶部半导体层的顶表面上方的高度。可以沉积另一个介电材料层，并且可以在顶部半导体层中形成另一个沟槽。可以使用另一选择性外延工艺将另一种半导体材料沉积到不同的高度。各种半导体材料部分可以被图案化以形成具有不同高度和/或不同组成的半导体鳍片。

7. 发明授权

US09536879B2 FinFET with constrained source-drain epitaxial region 有权
标题翻译：具有约束源极 - 漏极外延区域的FinFET
公开(公告)号：US09536879B2
公开(公告)日：2017-01-03
申请号：US14326745
申请日：2014-07-09
申请人： International Business Machines Corporation
发明人： Brian J. Greene , Arvind Kumar , Dan M. Mocuta
IPC分类号： H01L27/088 , H01L21/8234 , H01L29/66 , H01L29/78 , H01L29/165 , H01L21/3105 , H01L29/04 , H01L21/84
CPC分类号： H01L27/0886 , H01L21/31053 , H01L21/823418 , H01L21/823431 , H01L21/823437 , H01L21/823468 , H01L21/823814 , H01L21/823821 , H01L21/845 , H01L27/0924 , H01L29/045 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/6656 , H01L29/66636 , H01L29/7848 , H01L29/7853
摘要： A method includes forming a plurality of fins on a substrate, a gate is formed over a first portion of the plurality of fins with a second portion of the plurality of fins remaining exposed. Spacers are formed on opposite sidewalls of the second portion of the plurality of fins. The second portion of the plurality fins is removed to form a trench between the spacers. An epitaxial layer is formed in the trench. The spacers on opposite sides of the epitaxial layer constrain lateral growth of the epitaxial layer.
摘要翻译：一种方法包括在基板上形成多个散热片，在所述多个散热片的第一部分上形成栅极，所述多个散热片的第二部分保持露出。间隔件形成在多个翅片的第二部分的相对侧壁上。去除多个翅片的第二部分以在间隔件之间形成沟槽。在沟槽中形成外延层。外延层的相对侧上的间隔物限制外延层的横向生长。

8. 发明申请

US20150279692A1 SEMICONDUCTOR PROCESS TEMPERATURE OPTIMIZATION 有权
标题翻译： SEMICONDUCTOR PROCESS TEMPERATAL OPTIMIZATION
公开(公告)号：US20150279692A1
公开(公告)日：2015-10-01
申请号：US14230065
申请日：2014-03-31
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Brian J. Greene , Yue Liang , Xiaojun Yu
IPC分类号： H01L21/324 , H01L29/66 , H01L21/3205
CPC分类号： H01L21/324 , H01L21/32051 , H01L21/32055 , H01L29/66545
摘要： A method including forming a structure including a plurality of semiconductor devices surrounded by a dielectric layer such that a top surface of the dielectric layer is substantially flush with a top surface of the plurality of semiconductor devices, depositing a thermal optimization layer above the structure, patterning the thermal optimization layer such that a portion of the thermal optimization layer is removed from a above first region of the structure and another portion of the thermal optimization layer remains above a second region of the structure, the first region having a different thermal conductivity than the second region, and heating the structure, the patterned thermal optimization layer causing substantially uniform thermal absorption of the structure.
摘要翻译：一种方法，包括形成包括由电介质层包围的多个半导体器件的结构，使得电介质层的顶表面与多个半导体器件的顶表面基本齐平，在结构上方沉积热优化层，图案化所述热优化层使得所述热优化层的一部分从所述结构的上述第一区域移除，并且所述热优化层的另一部分保留在所述结构的第二区域的上方，所述第一区域具有不同于所述结构的第二区域的热导率第二区域，并且加热该结构，图案化热优化层引起结构的基本均匀的热吸收。

9. 发明授权

US09082877B2 Complementary metal oxide semiconductor (CMOS) device having gate structures connected by a metal gate conductor 有权
标题翻译：具有通过金属栅极导体连接的栅极结构的互补金属氧化物半导体（CMOS）器件
公开(公告)号：US09082877B2
公开(公告)日：2015-07-14
申请号：US14292312
申请日：2014-05-30
申请人： International Business Machines Corporation
发明人： Yue Liang , Dureseti Chidambarrao , Brian J. Greene , William K. Henson , Unoh Kwon , Shreesh Narasimha , Xiaojun Yu
IPC分类号： H01L21/8238 , H01L21/28 , H01L21/306 , H01L21/762 , H01L29/49
CPC分类号： H01L21/823871 , H01L21/28079 , H01L21/30604 , H01L21/76224 , H01L21/823878 , H01L29/4958
摘要： A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active region of the substrate are separated by from one another by an isolation region. A n-type semiconductor device is present on the first active region of the substrate, in which the n-type semiconductor device includes a first portion of a gate structure. A p-type semiconductor device is present on the second active region of the substrate, in which the p-type semiconductor device includes a second portion of the gate structure. A connecting gate portion provides electrical connectivity between the first portion of the gate structure and the second portion of the gate structure. Electrical contact to the connecting gate portion is over the isolation region, and is not over the first active region and/or the second active region.
摘要翻译：一种互补金属氧化物半导体（CMOS）器件，包括包括第一有源区和第二有源区的衬底，其中衬底的第一有源区和第二有源区中的每一个被隔离区彼此分开。 n型半导体器件存在于衬底的第一有源区上，其中n型半导体器件包括栅极结构的第一部分。 p型半导体器件存在于衬底的第二有源区上，其中p型半导体器件包括栅极结构的第二部分。连接栅极部分提供栅极结构的第一部分和栅极结构的第二部分之间的电连接。与连接栅极部分的电接触超过隔离区域，并且不在第一有源区域和/或第二有源区域之上。

10. 发明授权

US08941189B2 Fin-shaped field effect transistor (finFET) structures having multiple threshold voltages (Vt) and method of forming 有权
标题翻译：具有多个阈值电压（Vt）和成形方法的鳍状场效应晶体管（finFET）结构
公开(公告)号：US08941189B2
公开(公告)日：2015-01-27
申请号：US13735227
申请日：2013-01-07
申请人： International Business Machines Corporation
发明人： Murshed M. Chowdhury , Benjamin R. Cipriany , Brian J. Greene , Arvind Kumar
IPC分类号： H01L29/78 , H01L27/092 , H01L21/8238
CPC分类号： H01L27/0924 , H01L21/823821
摘要： Various embodiments include fin-shaped field effect transistor (finFET) structures that enhance work function and threshold voltage (Vt) control, along with methods of forming such structures. The finFET structures can include a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET). In some embodiments, the PFET has fins separated by a first distance and the NFET has fins separated by a second distance, where the first distance and the second distance are distinct from one another. In some embodiments, the PFET or the NFET include fins that are separated from one another by non-uniform distances. In some embodiments, the PFET or the NFET include adjacent fins that are separated by distinct distances at their source and drain regions.
摘要翻译：各种实施例包括增强功函数和阈值电压（Vt）控制的鳍状场效应晶体管（finFET）结构，以及形成这种结构的方法。 finFET结构可以包括p型场效应晶体管（PFET）和n型场效应晶体管（NFET）。在一些实施例中，PFET具有以第一距离分开的翅片，并且NFET具有以第二距离分开的翅片，其中第一距离和第二距离彼此不同。在一些实施例中，PFET或NFET包括通过不均匀距离彼此分离的翅片。在一些实施例中，PFET或NFET包括在其源极和漏极区域处被不同距离分开的相邻散热片。

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