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1. 发明授权

US09178010B2 Adsorption site blocking method for co-doping ALD films 有权
标题翻译：用于共掺杂ALD膜的吸附位点封闭方法
公开(公告)号：US09178010B2
公开(公告)日：2015-11-03
申请号：US13693901
申请日：2012-12-04
申请人： Intermolecular, Inc. , Elpida Memory, Inc.
发明人： Sandra Malhotra , Hanhong Chen , Wim Deweerd , Toshiyuki Hirota , Hiroyuki Ode
IPC分类号： H01L27/108 , H01L29/94 , H01L49/02 , H01L21/02 , C23C16/455 , H01L29/423
CPC分类号： H01L28/60 , C23C16/45534 , H01L21/02175 , H01L21/02178 , H01L21/02186 , H01L21/02189 , H01L21/02194 , H01L21/0228 , H01L27/10852 , H01L28/40 , H01L28/56 , H01L29/4234
摘要： A method for doping a dielectric material by pulsing a first dopant precursor, purging the non-adsorbed precursor, pulsing a second precursor, purging the non-adsorbed precursor, and pulsing a oxidant to form an intermixed layer of two (or more) metal oxide dielectric dopant materials. The method may also be used to form a blocking layer between a bulk dielectric layer and a second electrode layer. The method improves the control of the composition and the control of the uniformity of the dopants throughout the thickness of the doped dielectric material.
摘要翻译：一种用于通过脉冲第一掺杂剂前体掺杂电介质材料的方法，清洗未吸附的前体，脉冲第二前体，净化未吸附的前体，以及脉冲氧化剂以形成两个（或多个）金属氧化物的混合层电介质掺杂剂材料。该方法还可用于在体电介质层和第二电极层之间形成阻挡层。该方法改善了组合物的控制和掺杂介质材料整个厚度均匀性的控制。

2. 发明申请

US20130119513A1 Adsorption Site Blocking Method for Co-Doping ALD Films 审中-公开
标题翻译：共掺杂ALD膜的吸附场阻挡方法
公开(公告)号：US20130119513A1
公开(公告)日：2013-05-16
申请号：US13693901
申请日：2012-12-04
申请人： Intermolecular, Inc. , Elpida Memory , Inc.
发明人： Sandra Malhotra , Hanhong Chen , Wim Deweerd , Toshiyuki Hirota , Hiroyuki Ode
IPC分类号： H01L49/02
CPC分类号： H01L28/60 , C23C16/45534 , H01L21/02175 , H01L21/02178 , H01L21/02186 , H01L21/02189 , H01L21/02194 , H01L21/0228 , H01L27/10852 , H01L28/40 , H01L28/56 , H01L29/4234
摘要： A method for doping a dielectric material by pulsing a first dopant precursor, purging the non-adsorbed precursor, pulsing a second precursor, purging the non-adsorbed precursor, and pulsing a oxidant to form an intermixed layer of two (or more) metal oxide dielectric dopant materials. The method may also be used to form a blocking layer between a bulk dielectric layer and a second electrode layer. The method improves the control of the composition and the control of the uniformity of the dopants throughout the thickness of the doped dielectric material.
摘要翻译：一种用于通过脉冲第一掺杂剂前体掺杂电介质材料的方法，清洗未吸附的前体，脉冲第二前体，净化未吸附的前体，以及脉冲氧化剂以形成两个（或多个）金属氧化物的混合层电介质掺杂剂材料。该方法还可用于在体电介质层和第二电极层之间形成阻挡层。该方法改善了组合物的控制和掺杂介质材料整个厚度均匀性的控制。

3. 发明申请

US20130154057A1 Method for Fabricating a DRAM Capacitor 有权
标题翻译：制造DRAM电容器的方法
公开(公告)号：US20130154057A1
公开(公告)日：2013-06-20
申请号：US13738794
申请日：2013-01-10
申请人： Intermolecular, Inc. , Elpida Memory, Inc
发明人： Karthik Ramani , Hanhong Chen , Wim Deweerd , Nobumichi Fuchigami , Hiroyuki Ode
IPC分类号： H01L49/02
CPC分类号： H01L28/40 , H01G4/1218 , H01G4/33 , H01L28/60 , H01L28/75 , Y10T29/43 , Y10T29/435 , Y10T29/49002
摘要： A method for fabricating a dynamic random access memory (DRAM) capacitor stack is disclosed wherein the stack includes a first electrode, a dielectric layer, and a second electrode. The first electrode is formed from a conductive binary metal compound and the conductive binary metal compound is annealed in a reducing atmosphere to promote the formation of a desired crystal structure. The binary metal compound may be a metal oxide. Annealing the metal oxide (i.e. molybdenum oxide) in a reducing atmosphere may result in the formation of a first electrode material (i.e. MoO2) with a rutile-phase crystal structure. This facilitates the formation of the rutile-phase crystal structure when TiO2 is used as the dielectric layer. The rutile-phase of TiO2 has a higher k value than the other possible crystal structures of TiO2 resulting in improved performance of the DRAM capacitor.
摘要翻译：公开了一种用于制造动态随机存取存储器（DRAM）电容器堆叠的方法，其中堆叠包括第一电极，电介质层和第二电极。第一电极由导电二元金属化合物形成，并且导电二元金属化合物在还原气氛中退火以促进所需晶体结构的形成。二元金属化合物可以是金属氧化物。在还原气氛中退火金属氧化物（即氧化钼）可导致形成具有金红石相晶体结构的第一电极材料（即MoO 2）。当使用TiO 2作为电介质层时，这有助于金红石相晶体结构的形成。 TiO 2的金红石相具有比其他可能的TiO 2晶体结构更高的k值，从而改善了DRAM电容器的性能。

4. 发明申请

US20140187016A1 High Work Function, Manufacturable Top Electrode 有权
公开(公告)号：US20140187016A1
公开(公告)日：2014-07-03
申请号：US13727962
申请日：2012-12-27
申请人： INTERMOLECULAR, INC. , ELPIDA MEMORY, INC
发明人： Sandra G. Malhotra , Hanhong Chen , Wim Deweerd , Arthur Gevondyan , Hiroyuki Ode
IPC分类号： H01L49/02
CPC分类号： H01L29/92 , H01L28/65 , H01L28/75 , H01L51/0021 , H01L51/5206
摘要： Provided are MIM DRAM capacitors and methods of forming thereof. A MIM DRAM capacitor may include an electrode layer formed from a high work function material (e.g., greater than about 5.0 eV). This layer may be used to reduce the leakage current through the capacitor. The capacitor may also include another electrode layer having a high conductivity base portion and a conductive metal oxide portion. The conductive metal oxide portion serves to promote the growth of the high k phase of the dielectric layer.

5. 发明授权

US08476141B2 High performance dielectric stack for DRAM capacitor 有权
公开(公告)号：US08476141B2
公开(公告)日：2013-07-02
申请号：US13737785
申请日：2013-01-09
申请人： Intermolecular, Inc. , Elpida Memory, Inc.
发明人： Sandra Malhotra , Hanhong Chen , Wim Deweerd , Mitsuhiro Horikawa , Kenichi Koyanagi , Hiroyuki Ode , Xiangxin Rui
IPC分类号： H01L21/20 , H01L21/31
CPC分类号： H01L28/60 , H01L28/40 , H01L28/75
摘要： A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.

6. 发明申请

US20130143384A1 HIGH PERFORMANCE DIELECTRIC STACK FOR DRAM CAPACITOR 有权
公开(公告)号：US20130143384A1
公开(公告)日：2013-06-06
申请号：US13737785
申请日：2013-01-09
申请人： INTERMOLECULAR, INC. , ELPIDA MEMORY, INC
发明人： Sandra Malhotra , Hanhong Chen , Wim Deweerd , Mitsuhiro Horikawa , Kenichi Koyanagi , Hiroyuki Ode , Xiangxin Rui
IPC分类号： H01L49/02
CPC分类号： H01L28/60 , H01L28/40 , H01L28/75
摘要： A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.

7. 发明授权

US09224878B2 High work function, manufacturable top electrode 有权
标题翻译：高功能，可制造顶电极
公开(公告)号：US09224878B2
公开(公告)日：2015-12-29
申请号：US13727962
申请日：2012-12-27
申请人： Intermolecular, Inc. , Elpida Memory, Inc
发明人： Sandra G. Malhotra , Hanhong Chen , Wim Deweerd , Arthur Gevondyan , Hiroyuki Ode
IPC分类号： H01L21/20 , H01L29/92 , H01L49/02 , H01L51/52 , H01L51/00
CPC分类号： H01L29/92 , H01L28/65 , H01L28/75 , H01L51/0021 , H01L51/5206
摘要： Provided are MIM DRAM capacitors and methods of forming thereof. A MIM DRAM capacitor may include an electrode layer formed from a high work function material (e.g., greater than about 5.0 eV). This layer may be used to reduce the leakage current through the capacitor. The capacitor may also include another electrode layer having a high conductivity base portion and a conductive metal oxide portion. The conductive metal oxide portion serves to promote the growth of the high k phase of the dielectric layer.
摘要翻译：提供MIM DRAM电容器及其形成方法。 MIM DRAM电容器可以包括由高功函数材料（例如，大于约5.0eV）形成的电极层。该层可用于减少通过电容器的漏电流。电容器还可以包括具有高导电性基底部分和导电金属氧化物部分的另一个电极层。导电金属氧化物部分用于促进电介质层的高k相的生长。

8. 发明授权

US08836002B2 Method for fabricating a DRAM capacitor 有权
公开(公告)号：US08836002B2
公开(公告)日：2014-09-16
申请号：US13738794
申请日：2013-01-10
申请人： Intermolecular, Inc. , Elpida Memory, Inc
发明人： Karthik Ramani , Hanhong Chen , Wim Deweerd , Nobumichi Fuchigami , Hiroyuki Ode
IPC分类号： H01L27/108 , H01L29/94 , H01G4/12 , H01G4/33 , H01L49/02
CPC分类号： H01L28/40 , H01G4/1218 , H01G4/33 , H01L28/60 , H01L28/75 , Y10T29/43 , Y10T29/435 , Y10T29/49002
摘要： A method for fabricating a dynamic random access memory (DRAM) capacitor stack is disclosed wherein the stack includes a first electrode, a dielectric layer, and a second electrode. The first electrode is formed from a conductive binary metal compound and the conductive binary metal compound is annealed in a reducing atmosphere to promote the formation of a desired crystal structure. The binary metal compound may be a metal oxide. Annealing the metal oxide (i.e. molybdenum oxide) in a reducing atmosphere may result in the formation of a first electrode material (i.e. MoO2) with a rutile-phase crystal structure. This facilitates the formation of the rutile-phase crystal structure when TiO2 is used as the dielectric layer. The rutile-phase of TiO2 has a higher k value than the other possible crystal structures of TiO2 resulting in improved performance of the DRAM capacitor.

9. 发明授权

US08847397B2 High work function, manufacturable top electrode 有权
标题翻译：高功能，可制造顶电极
公开(公告)号：US08847397B2
公开(公告)日：2014-09-30
申请号：US13737263
申请日：2013-01-09
申请人： Intermolecular, Inc.
发明人： Sandra G. Malhotra , Hanhong Chen , Wim Deweerd , Arthur Gevondyan , Hiroyuki Ode
IPC分类号： H01L29/40 , H01L23/52 , H01L23/48 , H01L29/92 , H01L49/02 , H01L51/52
CPC分类号： H01L29/92 , H01L28/65 , H01L28/75 , H01L51/0021 , H01L51/5206
摘要： Provided are MIM DRAM capacitors and methods of forming thereof. A MIM DRAM capacitor may include an electrode layer formed from a high work function material (e.g., greater than about 5.0 eV). This layer may be used to reduce the leakage current through the capacitor. The capacitor may also include another electrode layer having a high conductivity base portion and a conductive metal oxide portion. The conductive metal oxide portion serves to promote the growth of the high k phase of the dielectric layer.
摘要翻译：提供MIM DRAM电容器及其形成方法。 MIM DRAM电容器可以包括由高功函数材料（例如，大于约5.0eV）形成的电极层。该层可用于减少通过电容器的漏电流。电容器还可以包括具有高导电性基底部分和导电金属氧化物部分的另一个电极层。导电金属氧化物部分用于促进电介质层的高k相的生长。

10. 发明授权

US08878269B2 Band gap improvement in DRAM capacitors 有权
标题翻译： DRAM电容器带隙改善
公开(公告)号：US08878269B2
公开(公告)日：2014-11-04
申请号：US13738831
申请日：2013-01-10
申请人： Intermolecular, Inc.
发明人： Hanhong Chen , Wim Deweerd , Sandra G. Malhotra , Hiroyuki Ode
IPC分类号： H01L27/108
CPC分类号： H01L28/40 , H01L21/02178 , H01L21/02181 , H01L21/02186 , H01L21/02189 , H01L21/02194 , H01L21/0228 , H01L27/1085 , H01L28/60
摘要： A method for forming a DRAM MIM capacitor stack having low leakage current and low EOT involves the use of an compound high k dielectric material. The dielectric material further comprises a dopant. One component of the compound high k dielectric material is present in a concentration between about 30 atomic % and about 80 atomic and more preferably between about 40 atomic % and about 60 atomic %. In some embodiments, the compound high k dielectric material comprises an alloy of TiO2 and ZrO2 and further comprises a dopant of Al2O3. In some embodiments, the compound high k dielectric material comprises an admixture of TiO2 and HfO2 and further comprises a dopant of Al2O3.
摘要翻译：用于形成具有低漏电流和低EOT的DRAM MIM电容器堆叠的方法涉及使用复合高k电介质材料。电介质材料还包括掺杂剂。复合高k介电材料的一个组分以约30原子％至约80原子之间的浓度存在，更优选约40原子％至约60原子％之间。在一些实施方案中，化合物高k介电材料包含TiO 2和ZrO 2的合金，并且还包含Al 2 O 3的掺杂剂。在一些实施方案中，化合物高k介电材料包含TiO 2和HfO 2的混合物，并且还包含Al 2 O 3的掺杂剂。

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