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1. 发明申请

US20140187016A1 High Work Function, Manufacturable Top Electrode 有权
公开(公告)号：US20140187016A1
公开(公告)日：2014-07-03
申请号：US13727962
申请日：2012-12-27
申请人： INTERMOLECULAR, INC. , ELPIDA MEMORY, INC
发明人： Sandra G. Malhotra , Hanhong Chen , Wim Deweerd , Arthur Gevondyan , Hiroyuki Ode
IPC分类号： H01L49/02
CPC分类号： H01L29/92 , H01L28/65 , H01L28/75 , H01L51/0021 , H01L51/5206
摘要： Provided are MIM DRAM capacitors and methods of forming thereof. A MIM DRAM capacitor may include an electrode layer formed from a high work function material (e.g., greater than about 5.0 eV). This layer may be used to reduce the leakage current through the capacitor. The capacitor may also include another electrode layer having a high conductivity base portion and a conductive metal oxide portion. The conductive metal oxide portion serves to promote the growth of the high k phase of the dielectric layer.

2. 发明授权

US08674479B2 Method for producing MIM capacitors with high K dielectric materials and non-noble electrodes 有权
标题翻译：用于制造具有高K电介质材料和非贵金属电极的MIM电容器的方法
公开(公告)号：US08674479B2
公开(公告)日：2014-03-18
申请号：US13902679
申请日：2013-05-24
申请人： Intermolecular, Inc. , Elpida Memory, Inc.
发明人： Hanhong Chen , Pragati Kumar
IPC分类号： H01L21/302
CPC分类号： H01L28/60 , H01L28/40
摘要： A method of producing a Metal-Insulator-Metal (MIM) capacitor stack through doping to achieve low current leakage and low equivalent oxide thickness is disclosed. A high K dielectric material is deposited on a non-noble electrode; the dielectric material is doped with oxides from group IIA. The dopant increases the barrier height of metal/insulator interface and neutralizes free electrons in dielectric material, therefore reduces the leakage current of MIM capacitor. The electrode may also be doped to increase work function while maintaining a rutile crystalline structure. The method thereby enhances the performance of DRAM MIM capacitor.
摘要翻译：公开了一种通过掺杂制造金属 - 绝缘体 - 金属（MIM）电容器堆叠以实现低电流泄漏和低等效氧化物厚度的方法。高K电介质材料沉积在非贵金属电极上; 电介质材料掺杂有IIA族的氧化物。掺杂剂增加了金属/绝缘体界面的势垒高度，并且中和了介电材料中的自由电子，从而降低了MIM电容器的漏电流。电极也可以掺杂以增加功函数，同时保持金红石晶体结构。该方法从而增强了DRAM MIM电容器的性能。

3. 发明授权

US08575671B2 Asymmetric MIM capacitor for DRAM devices 有权
标题翻译：用于DRAM器件的不对称MIM电容器
公开(公告)号：US08575671B2
公开(公告)日：2013-11-05
申请号：US13692460
申请日：2012-12-03
申请人： Intermolecular, Inc. , Elpida Memory, Inc.
发明人： Hanhong Chen , Hiroyuki Ode
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L28/65 , H01L27/10805 , H01L28/75
摘要： A bilayer second electrode for a MIM DRAM capacitor is formed wherein the layer of the electrode that is in contact with the dielectric layer (i.e. bottom layer) has a composition that is resistant to oxidation during subsequent anneal steps and have rutile templating capability. Examples include SnO2 and RuO2. The capacitor stack including the bottom layer is subjected to a PMA treatment to reduce the oxygen vacancies in the dielectric layer and reduce the interface states at the dielectric/second electrode interface. The other component of the bilayer (i.e. top layer) is a high work function, high conductivity metal or conductive metal compound.
摘要翻译：形成用于MIM DRAM电容器的双层第二电极，其中与电介质层（即底层）接触的电极层具有在随后的退火步骤期间耐氧化的组成并具有金红石模板能力。实例包括SnO 2和RuO 2。包括底层的电容器堆叠经受PMA处理以减少电介质层中的氧空位并降低电介质/第二电极界面处的界面态。双层的另一组分（即顶层）是高功函数，高导电性金属或导电金属化合物。

4. 发明授权

US08574999B2 Blocking layers for leakage current reduction in DRAM devices 有权
标题翻译：阻塞层用于DRAM器件的漏电流降低
公开(公告)号：US08574999B2
公开(公告)日：2013-11-05
申请号：US13738865
申请日：2013-01-10
申请人： Intermolecular Inc. , Elpida Memory, Inc
发明人： Sandra G. Malhotra , Hanhong Chen , Wim Y. Deweerd , Hiroyuki Ode
IPC分类号： H01L21/20 , H01L29/94
CPC分类号： H01L28/60 , H01L27/10852 , H01L28/40
摘要： A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer.
摘要翻译：用于形成具有低泄漏电流的DRAM MIM电容器堆叠的方法涉及使用用作促进随后沉积的介电层的高k相的模板的第一电极。高k电介质层包括可在随后的退火处理后结晶的掺杂材料。在电介质层上形成无定形阻挡层。选择阻挡层的厚度使得在随后的退火处理之后阻挡层保持无定形。在阻挡层上形成与阻挡层相容的第二电极层。

5. 发明授权

US08476141B2 High performance dielectric stack for DRAM capacitor 有权
公开(公告)号：US08476141B2
公开(公告)日：2013-07-02
申请号：US13737785
申请日：2013-01-09
申请人： Intermolecular, Inc. , Elpida Memory, Inc.
发明人： Sandra Malhotra , Hanhong Chen , Wim Deweerd , Mitsuhiro Horikawa , Kenichi Koyanagi , Hiroyuki Ode , Xiangxin Rui
IPC分类号： H01L21/20 , H01L21/31
CPC分类号： H01L28/60 , H01L28/40 , H01L28/75
摘要： A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.

6. 发明申请

US20130143384A1 HIGH PERFORMANCE DIELECTRIC STACK FOR DRAM CAPACITOR 有权
公开(公告)号：US20130143384A1
公开(公告)日：2013-06-06
申请号：US13737785
申请日：2013-01-09
申请人： INTERMOLECULAR, INC. , ELPIDA MEMORY, INC
发明人： Sandra Malhotra , Hanhong Chen , Wim Deweerd , Mitsuhiro Horikawa , Kenichi Koyanagi , Hiroyuki Ode , Xiangxin Rui
IPC分类号： H01L49/02
CPC分类号： H01L28/60 , H01L28/40 , H01L28/75
摘要： A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.

7. 发明申请

US20150228710A1 Methods to Improve Electrical Performance of ZrO2 Based High-K Dielectric Materials for DRAM Applications 有权
标题翻译：改善用于DRAM应用的ZrO2基高K介电材料的电性能的方法
公开(公告)号：US20150228710A1
公开(公告)日：2015-08-13
申请号：US14177118
申请日：2014-02-10
申请人： Elpida Memory, Inc , Intermolecular, Inc.
发明人： Xiangxin Rui , Hanhong Chen , Naonori Fujiwara , Imran Hashim , Kenichi Koyanagi
IPC分类号： H01L49/02 , H01L27/108
CPC分类号： H01L28/40 , H01G4/10 , H01G4/1236 , H01G4/33 , H01L27/10805 , H01L27/1085 , H01L28/56 , H01L28/75
摘要： A method for reducing the leakage current in DRAM MIM capacitors comprises forming a multi-layer dielectric stack from an amorphous highly doped material, an amorphous high band gap material, and a lightly-doped or non-doped material. The highly doped material will remain amorphous (
摘要翻译：用于减少DRAM MIM电容器中的漏电流的方法包括从非晶高掺杂材料，非晶高带隙材料和轻掺杂或非掺杂材料形成多层电介质叠层。退火步骤后，高掺杂材料将保持无定形（<30％结晶）。在退火步骤之后，高带隙材料将保持无定形（<30％结晶）。在退火步骤之后，轻掺杂或非掺杂材料将变成晶体（≥30％结晶）。高带隙材料形成在无定形高掺杂材料和轻掺杂材料和非掺杂材料之间，并提供通过多层电介质叠层的导电的中间屏障。

8. 发明授权

US08541868B2 Top electrode templating for DRAM capacitor 有权
公开(公告)号：US08541868B2
公开(公告)日：2013-09-24
申请号：US13665524
申请日：2012-10-31
申请人： Intermolecular, Inc. , Elpida Memory, Inc
发明人： Sandra G. Malhotra , Hanhong Chen , Wim Y. Deweerd , Hiroyuki Ode
IPC分类号： H01L21/02
CPC分类号： H01L28/40 , H01L21/02186 , H01L21/02194 , H01L21/0228 , H01L21/02304 , H01L21/02356 , H01L27/10852 , H01L28/75
摘要： A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. A metal oxide second electrode layer is formed above the dielectric layer. The metal oxide second electrode layer has a crystal structure that is compatible with the crystal structure of the dielectric layer. Optionally, a second electrode bulk layer is formed above the metal oxide second electrode layer.

9. 发明授权

US08541283B2 High performance dielectric stack for DRAM capacitor 有权
公开(公告)号：US08541283B2
公开(公告)日：2013-09-24
申请号：US13830282
申请日：2013-03-14
申请人： Intermolecular, Inc. , Elpida Memory, Inc
发明人： Sandra G. Malhotra , Hanhong Chen , Wim Y. Deweerd , Mitsuhiro Horikawa , Kenichi Koyanagi , Hiroyuki Ode , Xiangxin Rui
IPC分类号： H01L21/20 , H01L21/31
CPC分类号： H01L28/60 , H01L28/40 , H01L28/75
摘要： A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.

10. 发明申请

US20130071991A1 Electrode Treatments for Enhanced DRAM Performance 审中-公开
标题翻译：用于增强DRAM性能的电极处理
公开(公告)号：US20130071991A1
公开(公告)日：2013-03-21
申请号：US13677239
申请日：2012-11-14
申请人： Intermolecular, Inc. , Elpida Memory, Inc.
发明人： Xiangxin Rui , Takashi Arao , Hanhong Chen , Naonori Fujiwara , Edward Haywood , Toshiyuki Hirota , Takakazu Kiyomura , Kenichi Koyanagi , Sandra G. Malhotra
IPC分类号： H01L21/02
CPC分类号： H01L28/60 , H01L21/02 , H01L27/1085 , H01L28/40
摘要： A method for fabricating a dynamic random access memory capacitor is disclosed. The method may comprise depositing a first titanium nitride (TiN) electrode; creating a first layer of titanium dioxide (TiO2) on the first TiN electrode; depositing a dielectric material on the first layer of titanium dioxide; and depositing a second TiN electrode on the dielectric material.
摘要翻译：公开了一种用于制造动态随机存取存储器电容器的方法。该方法可以包括沉积第一氮化钛（TiN）电极; 在第一TiN电极上形成第一层二氧化钛（TiO 2）; 在第一层二氧化钛上沉积电介质材料; 以及在所述电介质材料上沉积第二TiN电极。

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