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1. 发明申请

US20160170930A1 Low cost low overhead serial interface for power management and other ICs 有权
标题翻译：用于电源管理和其他IC的低成本低开销串行接口
公开(公告)号：US20160170930A1
公开(公告)日：2016-06-16
申请号：US14570898
申请日：2014-12-15
申请人： Intel Corporation
发明人： SHELDON WENG , GEORGE E. MATTHEW , PAVAN KUMAR , WAYNE L. PROEFROCK , HARISH K. KRISHNAMURTHY , KRISHNAN RAVICHANDRAN
IPC分类号： G06F13/42 , G06F13/40 , G06F1/32 , G06F13/364
CPC分类号： G06F13/4282 , G06F1/26 , G06F1/3203 , G06F1/3253 , G06F13/364 , G06F13/404 , G06F2213/0052 , Y02D10/151
摘要： Methods and apparatus relating to low cost and/or low overhead serial interface for power management and other IC (Integrated Circuit) devices are described. In an embodiment, a unique address is assigned to each of a plurality of slave devices. The plurality of slave devices are coupled in a daisy chain configuration. And, any access directed at a first slave device from the plurality of slave devices is allowed based at least in part on comparison of an address of the first slave device and an address associated with the access. Other embodiments are also disclosed and claimed.
摘要翻译：描述了用于电源管理和其他IC（集成电路）设备的低成本和/或低开销串行接口的方法和装置。在一个实施例中，将唯一地址分配给多个从设备中的每一个。多个从设备以菊花链配置耦合。并且，至少部分地基于第一从设备的地址与与访问相关联的地址的比较，允许从多个从设备到第一从设备的任何接入。还公开并要求保护其他实施例。

2. 发明申请

US20160006350A1 TECHNIQUES FOR REDUCING SWITCHING NOISE AND IMPROVING TRANSIENT RESPONSE IN VOLTAGE REGULATORS 有权
标题翻译：降低开关噪声和改善电压稳压器瞬态响应的技术
公开(公告)号：US20160006350A1
公开(公告)日：2016-01-07
申请号：US14325310
申请日：2014-07-07
申请人： Intel Corporation
发明人： GEORGE E. MATTHEW , JESSICA GULLBRAND , KRISHNAN RAVICHANDRAN , WILLEM M. BELTMAN , KARTHIK SANKARANARAYANAN , SHELDON WENG , WAYNE L. PROEFROCK , HARISH K. KRISHNAMURTHY , PAVAN KUMAR
IPC分类号： H02M3/158 , H02M3/00
CPC分类号： H02M3/158 , H02M1/44 , H02M3/005 , H02M3/157 , H02M3/1582 , H02M2003/1566
摘要： Methods and apparatus relating to reducing switching noise and improving transient response in voltage regulators are described. In an embodiment, one or more pulses are inserted into an output waveform of a voltage regulator. The one or more pulses introduce multiple frequencies into the output waveform of the voltage regulator (e.g., to reduce acoustic noise). In another embodiment, the output voltage of a voltage regulator is modified in response to comparison of the output voltage with at least one of a plurality of threshold values. The plurality of threshold values includes an upper trigger point voltage value and a lower trigger point voltage value. Other embodiments are also disclosed and claimed.
摘要翻译：描述了降低开关噪声和改善稳压器瞬态响应的方法和装置。在一个实施例中，一个或多个脉冲被插入到电压调节器的输出波形中。一个或多个脉冲将多个频率引入电压调节器的输出波形（例如，以减少声学噪声）。在另一个实施例中，响应于输出电压与多个阈值中的至少一个的比较来修改电压调节器的输出电压。多个阈值包括上触发点电压值和下触发点电压值。还公开并要求保护其他实施例。

3. 发明申请

US20150113307A1 LINK POWER MANAGEMENT IN AN I/O INTERCONNECT 审中-公开
标题翻译：在I / O互连中链接电源管理
公开(公告)号：US20150113307A1
公开(公告)日：2015-04-23
申请号：US14506465
申请日：2014-10-03
申请人： Intel Corporation
发明人： Bradley Saunders , KRISHNAN RAVICHANDRAN
IPC分类号： G06F1/32 , G06F13/42
CPC分类号： G06F1/3278 , G06F1/325 , G06F1/3253 , G06F13/42 , Y02D10/151 , Y02D10/157
摘要： Described are embodiments of methods, apparatuses, and systems for link power management in an I/O interconnect. An apparatus for link power management in an I/O interconnect of a computer apparatus may include a switching fabric having a first switch and a second switch, configured to simultaneously transport first data packets over a first path of a link between a port of the first switch and a port of the second switch and second data packets over a second path of the link. The apparatus may include a power management unit configured to modify a power state of the port of the first switch based at least in part on relative power states of the first path and the second path. Other embodiments may be described and claimed.
摘要翻译：描述了用于I / O互连中的链路功率管理的方法，装置和系统的实施例。一种用于计算机设备的I / O互连中的链路功率管理的装置可以包括具有第一交换机和第二交换机的交换结构，其被配置为通过第一数据包的第一路径在第一交换机和第二交换机的端口以及链路的第二路径上的第二数据分组。该装置可以包括功率管理单元，其被配置为至少部分地基于第一路径和第二路径的相对功率状态来修改第一开关的端口的功率状态。可以描述和要求保护其他实施例。

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