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1. 发明申请

US20220200554A1 BUFFER CIRCUIT, RECEIVER, BASE STATION AND MOBILE DEVICE 有权
公开(公告)号：US20220200554A1
公开(公告)日：2022-06-23
申请号：US17131824
申请日：2020-12-23
申请人： Intel Corporation
发明人： Martin CLARA , Giacomo CASCIO
IPC分类号： H03F3/45 , H03F1/30
摘要： A buffer circuit is provided. The buffer circuit includes a Current Differencing Transconductance Amplifier (CDTA) comprising a first input node and a second input node each configured to receive a respective one of a first signal and a second signal. The buffer circuit further includes a first source follower circuit coupled to a first output node of the CDTA and configured to generate a first buffer output signal based on a first output signal of the CDTA. Additionally, the buffer circuit includes a second source follower circuit coupled to a second output node of the CDTA and configured to generate a second buffer output signal based on a second output signal of the CDTA. The buffer circuit further includes a first feedback path comprising at least one of a first resistive element and a first capacitive element. The first feedback path couples an output node of the first source follower circuit to the first input node of the CDTA. In addition, the buffer circuit includes a second feedback path comprising at least one of a second resistive element and a second capacitive element. The second feedback path couples an output node of the second source follower circuit to the second input node of the CDTA.

2. 发明公开

US20240006350A1 SEMICONDUCTOR PACKAGE, BASE STATION, MOBILE DEVICE AND METHOD FOR FORMING A SEMICONDUCTOR PACKAGE 审中-公开
公开(公告)号：US20240006350A1
公开(公告)日：2024-01-04
申请号：US17809985
申请日：2022-06-30
申请人： Intel Corporation
发明人： Ellis NEASE , Giacomo CASCIO , Marc Jan Georges TIEBOUT
IPC分类号： H01L23/66 , H01L23/498 , H01L21/48 , H01Q1/22
CPC分类号： H01L23/66 , H01L23/49822 , H01L23/49838 , H01L21/4857 , H01L21/486 , H01Q1/2283 , H01L2223/6622 , H01L2223/6627 , H01L2223/6638 , H01L2223/6655 , H01L2223/6677 , H01L2223/6688
摘要： A semiconductor package is provided. The semiconductor package includes a semiconductor die arranged within a housing of the semiconductor package. The semiconductor die holds a radio frequency circuit and a plurality of first electrical contacts. Additionally, the semiconductor package includes a plurality of second electrical contacts formed on the exterior of the housing to enable external electrical contacting of the semiconductor package. The semiconductor package further includes a plurality of transmission lines formed in or on a substrate of the semiconductor package. Each of the plurality of transmission lines couples a respective one of the plurality of first electrical contacts with a respective one of the plurality of second electrical contacts. At least one of the plurality of transmission lines is formed as a stepped transmission line transformer comprising a plurality of transmission line segments exhibiting different impedances to match a respective first impedance of the respectively coupled first electrical contact to a respective second impedance at the respectively coupled second electrical contact. The plurality of transmission line segments exhibit different spacings to one or more ground plane of the semiconductor package.

3. 发明公开

US20240007083A1 Multi-gain-step digital step attenuator 审中-公开
公开(公告)号：US20240007083A1
公开(公告)日：2024-01-04
申请号：US17809906
申请日：2022-06-30
申请人： Intel Corporation
发明人： Martin CLARA , Giacomo CASCIO , Erfan GHADERI , Marc Jan Georges TIEBOUT
IPC分类号： H03H11/24 , H04B1/40
CPC分类号： H03H11/245 , H04B1/40
摘要： A digital step attenuator for automatic gain control in a transceiver front-end. The digital step attenuator includes a series path coupled between an input port and an output port, a plurality of series shunt switches coupled in parallel to the series path, and a plurality of parallel paths coupled to the series path in parallel. The series path includes a plurality of series resistors coupled in series. Each series shunt switch is for by-passing a different set of one or more series resistors. Each parallel path includes a parallel resistor and a parallel shunt switch, and each parallel path is coupled to either the input port, the output port, or an internal node between two adjacent series resistors, in parallel. A plurality of different π-attenuators with a different topology are formed by selectively controlling the series shunt switches and the parallel shunt switches.

4. 发明申请

US20220200615A1 REFERENCE BUFFER CIRCUIT, ANALOG-TO-DIGITAL CONVERTER SYSTEM, RECEIVER, BASE STATION AND MOBILE DEVICE 有权
公开(公告)号：US20220200615A1
公开(公告)日：2022-06-23
申请号：US17131811
申请日：2020-12-23
申请人： Intel Corporation
发明人： Daniel GRUBER , Christian LINDHOLM , Martin CLARA , Giacomo CASCIO
IPC分类号： H03M1/08 , H03K19/003 , H03K19/0185 , H04B1/12
摘要： A reference buffer circuit for an analog-to-digital converter is provided. The reference buffer circuit includes a first input node configured to receive a first bias signal of a first polarity from a first signal line. Further, the reference buffer circuit includes a second input node configured to receive a second bias signal of a second polarity from a second signal line. Additionally, the reference buffer circuit includes a first output node configured to output a first reference signal of the first polarity. A first buffer amplifier is coupled between the first input node and the first output node. The reference buffer circuit includes in addition a second output node configured to output a second reference signal of the second polarity. A second buffer amplifier is coupled between the second input node and the second output node. Further, the reference buffer circuit includes a first coupling path comprising a first capacitive element. The first coupling path is coupled between the first output node and the second input node. In addition, the reference buffer circuit includes a second coupling path comprising a second capacitive element. The second coupling path is coupled between the second output node and the first input node.

5. 发明申请

US20220200613A1 INPUT BUFFER CIRCUIT, ANALOG-TO-DIGITAL CONVERTER SYSTEM, RECEIVER, BASE STATION, MOBILE DEVICE AND METHOD FOR OPERATING AN INPUT BUFFER CIRCUIT 有权
公开(公告)号：US20220200613A1
公开(公告)日：2022-06-23
申请号：US17131868
申请日：2020-12-23
申请人： Intel Corporation
发明人： Daniel GRUBER , Matteo CAMPONESCHI , Christian LINDHOLM , Martin CLARA , Giacomo CASCIO
IPC分类号： H03M1/06 , H03K3/02 , H04B1/16
摘要： An input buffer circuit for an analog-to-digital converter is provided. The input buffer circuit includes a buffer amplifier. The buffer amplifier includes a first input node and a second input node each configured to receive a respective one of a first input signal and a second input signal forming a differential input signal pair for the analog-to-digital converter. The buffer amplifier further includes a first output node and a second output node each configured to output a respective one of a first buffered signal and a second buffered signal. In addition, the input buffer circuit includes feedback circuitry. The feedback circuitry is configured to generate, based on the first buffered signal and the second buffered signal, a first feedback signal and a second feedback signal for mitigating a respective unwanted signal component at the first input node and the second input node related to a limited reverse isolation of the amplifier buffer. The feedback circuitry is further configured to supply the first feedback signal to the first input node and the second feedback signal to the second input node.

6. 发明公开

US20240007121A1 Device and method for reconfigurable common-mode feedback control in a receiver front end 审中-公开
公开(公告)号：US20240007121A1
公开(公告)日：2024-01-04
申请号：US17809575
申请日：2022-06-29
申请人： Intel Corporation
发明人： Martin CLARA , Giacomo CASCIO , Erfan GHADERI , Marc Jan Georges TIEBOUT
IPC分类号： H03M1/18
CPC分类号： H03M1/183
摘要： A radio frequency front-end (RF-FE) device with a reconfigurable common-mode feedback control. The device includes a plurality of RF-FE channels and a reconfiguration switch. An RF-FE channel includes a common-mode feedback loop. The common-mode feedback loop is configured to detect a common-mode signal in differential signals in the RF-FE channel and generate a feedback signal to set the common-mode signal. The reconfiguration switch is configured to couple common-mode feedback loops of two or more RF-FE channels based on an operation mode. The reconfiguration switch may be controlled to couple common-mode feedback loops of two or more RF-FE channels if the two or more RF-FE channels receive a same input signal and decouple common-mode feedback loops of two or more RF-FE channels if the two or more RF-FE channels receive different input signals.

7. 发明公开

US20240007117A1 METHOD AND SYSTEM FOR DIGITAL BACKGROUND OFFSET CORRECTION OF A COMPARATOR IN AN ANALOG-TO-DIGITAL CONVERTER 审中-公开
公开(公告)号：US20240007117A1
公开(公告)日：2024-01-04
申请号：US17809561
申请日：2022-06-29
申请人： Intel Corporation
发明人： Michael FULDE , Harneet KHURANA , Matteo CAMPONESCHI , Patrizia GRECO , Christian LINDHOLM , Martin CLARA , Giacomo CASCIO
IPC分类号： H03M1/06 , H03M1/10
CPC分类号： H03M1/0673 , H03M1/1023
摘要： A multi-step analog-to-digital converter (ADC). The ADC includes a sampling circuitry, a comparator, a trimming circuitry, and a DC offset actuator. The sampling circuitry is configured to sample an input analog signal. The comparator is for comparing the input analog signal sample or a residual component of the input analog signal sample to a reference value in each step. The trimming circuitry is configured to receive at least one low-order bit (e.g., a least significant bit and/or a second-least significant bit) of digital binary bits of each input analog signal sample and average the low order bit over a plurality of input analog signal samples and generate a control signal for correcting an input DC offset of the comparator based on an average value of the low-order bits. The DC offset actuator is configured to correct the input DC offset of the comparator based on the control signal.

8. 发明申请

US20220200616A1 Transceiver and method and system for controlling an analog-to-digital converter in an observation path in the transceiver 有权
公开(公告)号：US20220200616A1
公开(公告)日：2022-06-23
申请号：US17131819
申请日：2020-12-23
申请人： Intel Corporation
发明人： Matteo CAMPONESCHI , Albert MOLINA , Kannan RAJAMANI , Giacomo CASCIO , Christian LINDHOLM
IPC分类号： H03M1/10 , H04B1/40 , H04L5/00
摘要： A method and system for controlling an analog-to-digital converter (ADC) in an observation path in a transceiver. The transceiver includes a transmit path, a receive path, and an observation path. The observation path includes an analog buffer and an observation ADC. A controller generates a control signal to control sampling events at the observation ADC to activate the observation ADC at combined uniform and non-uniform sampling instants. The controller may also generate a second control signal indicating whether digital data obtained by the observation ADC is valid or not. The digital data generated by the observation ADC at non-uniform sampling instants is indicated as invalid and digital data generated by the observation ADC at uniform sampling instants is indicated as valid. The digital data indicated as invalid may be discarded and the digital data indicated as valid is used for calibration of the transmit path or the receive path.

9. 发明申请

US20220200545A1 SIGNAL ENVELOPE DETECTOR, OVERLOAD DETECTOR, RECEIVER, BASE STATION AND MOBILE DEVICE 有权
公开(公告)号：US20220200545A1
公开(公告)日：2022-06-23
申请号：US17131962
申请日：2020-12-23
申请人： Intel Corporation
发明人： Martin CLARA , Giacomo CASCIO
IPC分类号： H03F3/19 , H03F3/24
摘要： A signal envelope detector is provided. The signal envelope detector includes an input node configured to receive an input signal. Further, the signal envelope detector includes a capacitive voltage divider coupled to the input node and configured to generate an attenuated input signal by voltage division of the input signal. The signal envelope detector additionally includes a source follower transistor coupled between a first node configured to receive a first voltage supply signal and a second node configured to receive a second voltage supply signal. A gate terminal of the source follower transistor is coupled to the capacitive voltage divider and configured to receive the attenuated input signal. The signal envelope detector includes a rectifier circuit configured to receive and rectify an output signal of the source follower transistor. In addition, the signal envelope detector includes a low-pass filter coupled to the rectifier circuit and configured to generate an envelope signal indicative of a rectified envelope of the input signal by low-pass filtering of an output signal of the rectifier circuit.

10. 发明公开

US20230208427A1 Successive approximation register analog-to-digital converter 审中-公开
公开(公告)号：US20230208427A1
公开(公告)日：2023-06-29
申请号：US17645755
申请日：2021-12-23
申请人： Intel Corporation
发明人： Michael FULDE , Harneet KHURANA , Matteo CAMPONESCHI , Patrizia GRECO , Christian LINDHOLM , Martin CLARA , Giacomo CASCIO
IPC分类号： H03M1/06 , H03M1/00
CPC分类号： H03M1/0682 , H03M1/002
摘要： A successive approximation register (SAR) analog-to-digital converter (ADC) includes a plurality of differential capacitive digital-to-analog converters (C-DACs), comparators, and an SAR controller. Each differential C-DAC comprises a pair of C-DACs for positive and negative polarities and each C-DAC comprises a capacitor array. A capacitor for each bit position may include a pair of equal-sized capacitors. Each outer comparator is coupled to one of the differential C-DACs and the middle comparator is coupled to a differential output node pair of C-DACs from two differential C-DACs. The SAR controller generates a control signal for the differential C-DACs for each conversion step based on outputs of the comparators. The outputs of the comparators are provided to the differential C-DACs as the control signal without encoding. Single-bit/cycle shorting switches for shorting top plates of capacitors of the C-DACs of same polarity may be closed during a single-bit/cycle conversion.

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